121–130 of 141 posts
There are 10 kind of people. Those who like to drag from the input back to the output and those who prefer to drag from the output to the input.
Author here: The reason you drag from the input rather than output is that a pin can have only one input.
I know digital logic, yet was perplexed by the odd definition of D flip-flop this game uses with both "store" and "clock" inputs, which matches none of the standard variants of DFFs: https://en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip... Edit: this continues on with the counter level, where you can use the register but it does not behave like the typical set of edge-triggered flip-flops (or transparent latch…
Not that this will ever matter for someone who isn't a circuit designer, but the "optimal" solution for the latch is actually really bad. If you use a "select" block (which should really be called "mux") and tie the output to the input, you create a race condition. If the data input is 1, and you change set from 1 to 0, the output can actually glitch to 0 for a very short period of time, which is a big no-no. (If you…
Since the latch is only used as a component of the flip-flip and edge sensitive logic does not care about glitches except on the clock line or any asynchronous set/resets (which are not used in this design) I find that rather unimportant. Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters. For a design that uses latches as sta…
I didn't go through the entire game, so its entirely possible that it would not affect this particular "design". But as its far more educational than practical, I think its still worth mentioning.
> Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters.
I'm curious where you've seen that implementation because I've never seen anything like that. Most of what I've seen uses two tri-state inverter latches.
Nicely done! If the author is reading, care to share any details on what stack or libraries were used?
Author here - It uses TypeScript and the Angular framework. Not because I prefer Angular in particular but because I had to learn it anyway for a work-related project. I think TypeScript is great.
Earlier quoted context omitted.
Since the latch is only used as a component of the flip-flip and edge sensitive logic does not care about glitches except on the clock line or any asynchronous set/resets (which are not used in this design) I find that rather unimportant. Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters. For a design that uses latches as sta…
In practical designs, flip flop outputs are regularly used as clock inputs and asynchronous set/reset inputs. If you used this latch as the output latch in a flip flop, it would glitch on the falling edge of the flip flop clock. I didn't go through the entire game, so its entirely possible that it would not affect this particular "design". But as its far more educational than practical, I think its still worth mentio…
Earlier quoted context omitted.
In practical designs, flip flop outputs are regularly used as clock inputs and asynchronous set/reset inputs. If you used this latch as the output latch in a flip flop, it would glitch on the falling edge of the flip flop clock. I didn't go through the entire game, so its entirely possible that it would not affect this particular "design". But as its far more educational than practical, I think its still worth mentio…
Not the one you're replying to, but look up "transmission gate latch". As for an actual processor that uses them, see the RCA CDP1802, for which a die photo and reverse engineered gate-level schematic are available.
Definitely have seen tgate flip flops. They seem to be less in fashion now though I'm not exactly sure why.
Building circuits is neat, but I think this has some problems as a game: 1. It seems to only let you save one solution for each level, even though there are two optimization goals. It should let you save one for fewest components and one for fewest NAND gates. 2. It's not really clear how NAND gate counts work in later levels where you're using potentially non-optimal components you've built? Like does it count each…
Author here - thank you for the feedback! The nand-count is based on how you built the components involved. So optimizing a component will have have cascading effects. "This is the simplest solution!" means the solution with fewest individual components on the canvas. I realize the text could be clearer.