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An ARM killer from IIT-M?

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Re: An ARM killer from IIT-M?

#121

Post by gsmadhusudan »

ksec wrote: post #26

The Actual ARM license and IP, is relatively tiny in overall cost of the chip. It is a very small amount of money for time to market and ecosystem. ARMv8 ( Specifically the aarch64 part ) is like a clean start. I doubt RISC-V offer any advantage, especially we should now know the uArch is only tiny part of the equation, the implementation matters a lot. Apart from the fear of lock in or ARM suddenly hike the price 10…

The Risc-V ISA is far more modular and extensible. Also we needed the 128 bit support for our NVM storage research and single address space OS work. No MMU, T-ISA based security, VIVT caches. Other govt projects do have ARM licenses, we chose not to go that way for purely technical reasons. Our lab does have academic collaboration with ARM.

Re: An ARM killer from IIT-M?

#122

Post by wsxcde »

signa11 wrote: post #38
wsxcde wrote: post #34

Earlier quoted context omitted.

Why do Baidu and Tencent count, but Infosys and TCS not count? Each of these have companies with >10B USD of revenue, so it's not like the Chinese companies are any larger. And don't tell me, it's because of the difference between product and service companies, because that is meaningless distinction from the perspective of a hardware-marker. They all need hardware to run on and arguably a service company needs more.…

> Why do Baidu and Tencent count, but Infosys and TCS not count? Each of these have companies with >10B USD of revenue... umm, probably because both of these companies are not exactly known for their cutting edge r&d.

On the contrary, both Infosys Research and the TCS Innovation Lab are organically growing research labs who have been steadily producing quality scholarly work for some years now.

I'm not aware of anything of note coming from Baidu research. All they've done is a splashy celebrity hire of Andrew Ng, which is the exact opposite of how one would set up a serious research organization.

Re: An ARM killer from IIT-M?

#123

Post by wsxcde »

TheArcane wrote: post #77
wsxcde wrote: post #34

Earlier quoted context omitted.

Why do Baidu and Tencent count, but Infosys and TCS not count? Each of these have companies with >10B USD of revenue, so it's not like the Chinese companies are any larger. And don't tell me, it's because of the difference between product and service companies, because that is meaningless distinction from the perspective of a hardware-marker. They all need hardware to run on and arguably a service company needs more.…

> the US is much less attractive destination The US is still extremely attractive, especially for STEM talent.Indian educated migrants think of Trump as a temporary phase; and given how migrants power the American tech industry, they feel impervious to most Trump related threats.

If we're trading anecdotes, then I'm an Indian-educated migrant with a PhD from one elite US school who is current a postdoc at another elite US school and I've accepted an offer from an IIT.

Trump is by no means a temporary phase. The demographic trends that led to Trump will continue for a long while.

The "big sort" means that 70% of US population will be represented by 30 senators by 2050. Guess which party the other 70 senators representing primarily rural populations will belong to? The republican advantage in the electoral college will continue to grow as the rust belt becomes older and whiter. The supposed democratic flips of Arizona, Georgia and Texas due to rising Latino population are still far away in future and in the meantime, republican voter id legislation and gerrymandering of state-level districts to control state-level legislatures will ensure they remain red for the foreseeable future.

What all this really means is that the current situation -- where winning the primary is far more important than the general for republican politicians -- will continue for at least a decade or two more. Which means we WILL have more Trumps. The scary part of this is that the next guy won't be as incompetent at implementing his own agenda as this one.

Re: An ARM killer from IIT-M?

#124

Post by gsmadhusudan »

KMag wrote: post #113
bonzini wrote: post #45

Earlier quoted context omitted.

That's what some people were doing with SuperH; I don't know how the project has progressed. https://lwn.net/Articles/647636/ [If you wanted to resurrect the Alpha, though, please do not resurrect the crazy memory consistency semantics, where you need to put a full memory barrier between r0 = load(&x); r1 = load(r0);

Do you have any pointers to good documentation on the Alpha memory semantics? The memory semantics are of course so lax so that the processor doesn't need to check the computed addresses of all in-flight stores before issuing a concurrent memory operation. My understanding is that it's mostly a footgun for assembly programmers, but I'd love to see any estimates of the speed and power efficiency benefits of the lax me…

This is one of the raging debates within the RISC-V group and elsewhere. Is weak memory semantics really worth it or can x86 style TSO be implemented optimally.Lot of anecdotal evidence but no conclusive experiment. As part of our work we hope to try multiple memory models in our I-class and get some definitive answers.RISC-V by the way supports ARM/PPC style weak memory model or optionally an x86 style TSO.

Re: An ARM killer from IIT-M?

#125

Post by bonzini »

gsmadhusudan wrote: post #124
KMag wrote: post #113

Earlier quoted context omitted.

Do you have any pointers to good documentation on the Alpha memory semantics? The memory semantics are of course so lax so that the processor doesn't need to check the computed addresses of all in-flight stores before issuing a concurrent memory operation. My understanding is that it's mostly a footgun for assembly programmers, but I'd love to see any estimates of the speed and power efficiency benefits of the lax me…

This is one of the raging debates within the RISC-V group and elsewhere. Is weak memory semantics really worth it or can x86 style TSO be implemented optimally.Lot of anecdotal evidence but no conclusive experiment. As part of our work we hope to try multiple memory models in our I-class and get some definitive answers.RISC-V by the way supports ARM/PPC style weak memory model or optionally an x86 style TSO.

ARM/PPC is fine, but Alpha took it too far in my opinion (and also didn't have a read memory barrier instruction---nowadays acquire and release memory barriers would probably be preferrable).

Re: An ARM killer from IIT-M?

#126

Post by inteleng »

PinguTS wrote: post #50
inteleng wrote: post #43

Earlier quoted context omitted.

I'm not sure why pedroaraujo is being downvoted other than in response to his criticism of HN topcommenter Chuck McManis. Pedro is correct; toy CPUs , like what Chuck mentioned building, are so trivial that undergraduate students can build functioning models of them in a few days or hours. They are quite literally thousands of times less complex than the CPUs (even RISC arches) that are discussed in the article. I al…

It seems both of you haven't read the article itself. The new CPU design is not about high-end CPU you expect from Intel or AMD. It is about CPUs for the IoT. We are talking about Cortex-M alike CPUs you find in micro-controllers from Infineon, NXP, Renesas, and alike. BTW there is competition to the ARM design. It is the micro-controllers from NXP former Freescale, which have their own CPU design heavily used in aut…

Do you think ARMs don't have branch predictors or multi-level caching? Did you know some supercomputers are being designed around ARM computers? x86_64 is not king anymore.

Re: An ARM killer from IIT-M?

#127

Post by kjs3 »

pertymcpert wrote: post #56
inteleng wrote: post #43

Earlier quoted context omitted.

I'm not sure why pedroaraujo is being downvoted other than in response to his criticism of HN topcommenter Chuck McManis. Pedro is correct; toy CPUs , like what Chuck mentioned building, are so trivial that undergraduate students can build functioning models of them in a few days or hours. They are quite literally thousands of times less complex than the CPUs (even RISC arches) that are discussed in the article. I al…

You have been exceptionally rude to a commentor that has not been rude at all but given some insight about the true difficulties of the making a viable CPU business.

Not to mention a commentor with an industry reputation in the field, whereas the replier has none.

Re: An ARM killer from IIT-M?

#128

Post by inteleng »

kstenerud wrote: post #54
inteleng wrote: post #43

Earlier quoted context omitted.

I'm not sure why pedroaraujo is being downvoted other than in response to his criticism of HN topcommenter Chuck McManis. Pedro is correct; toy CPUs , like what Chuck mentioned building, are so trivial that undergraduate students can build functioning models of them in a few days or hours. They are quite literally thousands of times less complex than the CPUs (even RISC arches) that are discussed in the article. I al…

When you post a rude reply about a topic not many people have expertise in, the only thing up/downvoters have to go on is how you carry yourself. My first gut reaction to his reply was "troll."

That's fair. I suppose I overestimated the significance of Chuck's username.

Re: An ARM killer from IIT-M?

#129

Post by inteleng »

ChuckMcM wrote: post #109
inteleng wrote: post #43

Earlier quoted context omitted.

I'm not sure why pedroaraujo is being downvoted other than in response to his criticism of HN topcommenter Chuck McManis. Pedro is correct; toy CPUs , like what Chuck mentioned building, are so trivial that undergraduate students can build functioning models of them in a few days or hours. They are quite literally thousands of times less complex than the CPUs (even RISC arches) that are discussed in the article. I al…

"ChuckMcM's comment is yet another disappointing step toward the total calcification of this forum. It's not a commentary on the article; it simply states, lazily, and ignorantly, that whatever it is they're attempting at IIT-M, it can't be too hard. What an an incredibly condescending and blasé thing to say, especially on a public forum where what you say can't be erased." I suppose it could be deleted though. I wou…

It wouldn't really fit with the PR narrative for them to just license IP from ARM, and they probably wouldn't develop nearly as much technical knowledge as they would developing the architecture themselves.

Aside, I hope my comment didn't seem too abrasive. It's hard not to get attached to something you work closely on most of your life.

Re: An ARM killer from IIT-M?

#130

Post by ChuckMcM »

inteleng wrote: post #129
ChuckMcM wrote: post #109

Earlier quoted context omitted.

"ChuckMcM's comment is yet another disappointing step toward the total calcification of this forum. It's not a commentary on the article; it simply states, lazily, and ignorantly, that whatever it is they're attempting at IIT-M, it can't be too hard. What an an incredibly condescending and blasé thing to say, especially on a public forum where what you say can't be erased." I suppose it could be deleted though. I wou…

It wouldn't really fit with the PR narrative for them to just license IP from ARM, and they probably wouldn't develop nearly as much technical knowledge as they would developing the architecture themselves. Aside, I hope my comment didn't seem too abrasive. It's hard not to get attached to something you work closely on most of your life.

I expect you are exactly correct on the narrative angle. Which is sad because there are so many great stories of people who worked on someone else's technology and then branched out and started their own. The Fairchild => Intel story is just one such example. And it makes me sad when the 'narrative' interferes with the goal. If the goal is to develop a vibrant CPU/semiconductor capability in India then that effort is cultivated by minimizing risk where possible and leveraging other work. And leveraging ARM would be a great way to train up on all the things you have to have/do in order to support a range of offerings for a given ISA.

As for abrasiveness, I read it as a passion more than insult. I also read it as a signal of frustration and I like to understand the roots of the frustration in order to improve things.

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