Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

anandtech.com

Post reply on HN
Print view View original

121–130 of 169 posts

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#121

Post by agumonkey »

PeCaN wrote: post #112
agumonkey wrote: post #86

Earlier quoted context omitted.

My shallow understanding of big servers and IBM Z series amounted to "lots of dedicated IO processors". Seems like "mainstream" caught up with big blue.

Pretty much. Mainframes have been very I/O oriented from the start. Channel I/O (more or less DMA) with dedicated channel programs and processors can be very high-throughput.

Also I suppose it frees the logic processors from all IO (caching too?) related processing and allow for fancier strategies downstream .. (all guess fest)

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#122

Post by leonroy »

simplyinfinity wrote: post #74
striking wrote: post #48

Earlier quoted context omitted.

The Ryzen 7 1800X has a TDP of 95W and beats the 140W Intel i7-6900K by 4% in performance. They've made some huge jumps in power efficiency. I don't know if AMD will make a new architecture or not, but I can't see why they wouldn't just release 32 Ryzen cores side-by-side and underclocked at the stock configuration.

The thermal design power is the maximum amount of heat generated by a computer chip or component that the cooling system in a computer is designed to dissipate in typical operation. TDP =/= power consumed

As far as TDP goes, the transferrence of electrical energy to heat is equivalent to that of a space heater as Puget Systems demonstrated here: https://www.pugetsystems.com/labs/articles/Gaming-PC-vs-Spac...

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#123

Post by [deleted] »

loeg wrote: post #119
simplyinfinity wrote: post #74

Earlier quoted context omitted.

The thermal design power is the maximum amount of heat generated by a computer chip or component that the cooling system in a computer is designed to dissipate in typical operation. TDP =/= power consumed

> TDP =/= power consumed Where do you think the heat comes from? Or where do you think the power that doesn't turn into heat goes?

[deleted]

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#124

Post by astrodust »

arca_vorago wrote: post #80
kannanvijayan wrote: post #61

Earlier quoted context omitted.

I did sequence-based bioinformatics back around 2006 or so. Very few of the operations used GPU. Things may have changed since I was working there, but the work at the time wasn't suited for a GPU architecture. Initial step was sequence cleanup, which is a hidden markov model executed over a collection of sequences of varying length, so hard to parallelize. Sequence annotation is embarassingly parallel on a per-libra…

"Lots of cores, lots of threads, and lots of main memory. That was the key." Very much this. Which is why I ended up theorycrafting that the AMD many core CPU's would be so useful.

Xeon Phi tried to crack this nut and seems to have mostly failed so far.

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#125

Post by astrodust »

noir_lord wrote: post #78
CreRecombinase wrote: post #57

Earlier quoted context omitted.

It's quite rare to find GPUs being used in genetics.

Is that because the workloads are fundamentally unsuitable for current GPU architectures or because no one has took a good stab at it yet? I know very little about computation genetics/biology but it sounds interesting.

FPGA type applications will probably pay way bigger dividends than GPU acceleration ever will.

GPUs excel at problems where you can apply exactly the same logic to lots of data in parallel. CPUs can handle branching cases, where each operation requires a lot of decisions, a lot better.

Sufficiently large FPGA chips could accelerate certain parts of the workflow, if not the whole thing, since they're extremely good at branching in parallel. This is why early FPGA Bitcoin implementations blew the doors off of any GPU solution, each round of the SHA hashing process can be run in parallel on sequentially ordered data if you organize it correctly.

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#126

Post by AYBABTME »

istoica wrote: post #47
drzaiusapelord wrote: post #33

Earlier quoted context omitted.

>And AMD should dump SHA1 acceleration in the next generation. The cost to have that on silicon is probably close to zero. If you think SHA1 is just going to magically disappear because you want it to, well, you'll be in for a SHA1 sized surprise. Our grandkids will still have SHA1 acceleration. >ARMv8 has had it for like 2-3 years now... Because ARM cores don't remotely have the CPU heft an Intel x86/64 chip has, so…

Why should it be dropped ? Isn't it just a hash function ?

Short story: because its role as a crypto hash function is sort of obsolete given that it's been proven to be broken, and faster, more secure alternatives exist.

But for all practical purposes, SHA1 isn't about to disappear. MD5 has been shown to be broken since forever and people still write new code using it today.

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#127

Post by p1esk »

drewg123 wrote: post #120
wtallis wrote: post #40

Earlier quoted context omitted.

Intel's largest CPUs are already explicitly NUMA on a single socket. They call it Cluster On Die: http://images.anandtech.com/doci/10401/03%20-%20Architectura...

Very true, I should have mentioned that. At least for us, COD doesn't seem to impact our performance at all, while NUMA does. I'm hoping that Naples is the same for us. However, there is an important difference. AMD seems to be putting multiple dies into the same package , whereas Intel seems to have (as the Cluster on Die name implies) everything on the same die. So my fear is that the interconnect between dies may…

Sounds like your application is latency sensitive, and not bandwidth sensitive, take a look at the graphs towards the end of this article:

https://www.starwindsoftware.com/blog/numa-and-cluster-on-di...

There's not much difference in memory bandwidth between crossing domains on the same die (COD) vs crossing domains system wide (accessing memory for a different socket). What kind of computation are you running?

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#128

Post by [deleted] »

mtgx wrote: post #49
chx wrote: post #39

Earlier quoted context omitted.

There's opportunity cost to consider. Google has Skylake-E now which is not even available at retail yet.

Well, it also seems that Intel prioritized its customers. If I were Amazon or Microsoft (the rumors said Google and Facebook were the priority customers), I would get Naples just to spite Intel (it doesn't hurt that AMD's Naples likely offers better perf/$, too, though): https://semiaccurate.com/2016/11/17/intel-preferentially-off...

[deleted]

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#129

Post by arca_vorago »

deepnotderp wrote: post #91
arca_vorago wrote: post #80

Earlier quoted context omitted.

"Lots of cores, lots of threads, and lots of main memory. That was the key." Very much this. Which is why I ended up theorycrafting that the AMD many core CPU's would be so useful.

Hmmm, isn't deep learning starting to pick up for genetics? No idea if it is actually is, but everyone in DL seems to be talking about it, I thought I'd ask someone actually in bioinformatics :)

I wish I could say, I it's been a good two+ years since I left the genetics company, so I've been in a different industry for a while. I would say theres probably plenty of room, if people start taking more novel approaches that use more data, eg, full microbiome analysis. Also, I was just a sysadmin, so I don't really know anything other than keeping systems running, so take what I say with a grain of salt.
Post reply on HN