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AMD's Turin: 5th Gen EPYC Launched

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Re: AMD's Turin: 5th Gen EPYC Launched

#111

Post by bee_rider »

smolder wrote: post #77

The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that are based on "per-core" licensing. It really doesn't make much sense to have so few cores at such an expense, otherwise. Does Oracle still use this style of licensing? If so, they need to knock it off. The only other thing I can think of is some purpose like HFT…

512 MB of cache, wow.

A couple years ago I noticed that some Xeons I was using had a much cache as the ram in the systems I had growing up (millennial, so, we’re not talking about ancient commodores or whatever; real usable computers that could play Quake and everything).

But 512MB? That’s roomy. Could Puppy Linux just be held entirely in L3 cache?

Re: AMD's Turin: 5th Gen EPYC Launched

#112

Post by hedora »

bee_rider wrote: post #111
smolder wrote: post #77

The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that are based on "per-core" licensing. It really doesn't make much sense to have so few cores at such an expense, otherwise. Does Oracle still use this style of licensing? If so, they need to knock it off. The only other thing I can think of is some purpose like HFT…

512 MB of cache, wow. A couple years ago I noticed that some Xeons I was using had a much cache as the ram in the systems I had growing up (millennial, so, we’re not talking about ancient commodores or whatever; real usable computers that could play Quake and everything). But 512MB? That’s roomy. Could Puppy Linux just be held entirely in L3 cache?

I wonder if you can boot it without populating any DRAM sockets.

Re: AMD's Turin: 5th Gen EPYC Launched

#113

Post by jodrellblank »

Sakos wrote: post #46
stonethrowaway wrote: post #29

[flagged]

This is lazy criticism and honestly, I'll take a name like Epyc over Intel Core Ultra 7 258V or Ryzen AI 9 HX 370. > Looks like the folks downvoting me are massive, massive fans of that THREADRIPPER architecture. Yes, it must be everybody else, not your comment, which is the pinnacle of deep analysis. Get real, dude.

Intel's naming isn't great, but it's pretty clear. Look at Wikipedia's List of Intel Processors[1] and for 14 generations since 2010, the higher the model number, the faster the processor. The model number like 13700 starts with the generation (13th) and then place in that (700 is upper-mid). Then a capital letter indicating something about form factor.

Compare with List of AMD processors[2] and a "70xx" model could be a Zen Naples Epic, A Zen 2 Mendocino Ryzen, a Zen 2 Rome Epyc, a Barceló-R Ryzen Zen 3, a Milan Epyc Zen 3, a Rembrandt-R Zen 3+, a Zen 4 Raphael Ryzen or Storm Peak Threadripper, or a laptop Ryzen. Wikipedia people can't even put these into a table to compare them, it's pages of random names and overlapping/re-used numbers.

Apple, as usual, have M1, M2, M3 and each one has plain/pro/max/ultra.

[1] https://en.wikipedia.org/wiki/List_of_Intel_processors#Lates...

[2] https://en.wikipedia.org/wiki/List_of_AMD_processors

Re: AMD's Turin: 5th Gen EPYC Launched

#114

Post by kjs3 »

chx wrote: post #98
p_l wrote: post #67

Earlier quoted context omitted.

first dual core server chips show up generally available in 2001 with IBM POWER4, then HP PA-RISC ones in 2004, and then Opterons which was followed by "emergency" design of essentially two "sockets" on one die of of NetBurst dual core systems.

Also, I raised the question at https://retrocomputing.stackexchange.com/q/30743/3722 and one of the answers points out the 1984 Rockwell R65C29 Dual CMOS Microprocessor. It was two standard 6502 on the same die using the same bus to access the same memory... and of course IBM mainframes did it decades before.

If we're going that direction, National Semiconductor had a 2 'core' COPS4 processor in 1981[1]. I have some in a tube somewhere (unused).

[1] https://www.cpushack.com/2014/08/25/national-semiconductor-c...

Re: AMD's Turin: 5th Gen EPYC Launched

#115

Post by bee_rider »

hedora wrote: post #112
bee_rider wrote: post #111

Earlier quoted context omitted.

512 MB of cache, wow. A couple years ago I noticed that some Xeons I was using had a much cache as the ram in the systems I had growing up (millennial, so, we’re not talking about ancient commodores or whatever; real usable computers that could play Quake and everything). But 512MB? That’s roomy. Could Puppy Linux just be held entirely in L3 cache?

I wonder if you can boot it without populating any DRAM sockets.

I would be pretty curious about such a system. Or, maybe more practically, it might be interesting to have a system pretends the L3 cache is ram, and the ram is the hard drive (in particular, ram could disguise itself as the swap partition, to so the OS would treat is as basically a chunk of ram that it would rather not use).

Re: AMD's Turin: 5th Gen EPYC Launched

#116

Post by kjs3 »

Uvix wrote: post #87
sph wrote: post #75

Earlier quoted context omitted.

They sell this vendor lock-in "feature" as enhanced security?

Yes. It keeps the board from booting if the firmware is replaced with a version not signed by the board manufacturer (i.e. so an attacker can’t replace it with a version that does nefarious things). Preventing CPU reuse in other boards is just an (unintentional?) side effect.

The cynic would say the security implications are the side effect, since selling more, new chips is the goal.

Re: AMD's Turin: 5th Gen EPYC Launched

#117

Post by compressedgas »

bee_rider wrote: post #115
hedora wrote: post #112

Earlier quoted context omitted.

I wonder if you can boot it without populating any DRAM sockets.

I would be pretty curious about such a system. Or, maybe more practically, it might be interesting to have a system pretends the L3 cache is ram, and the ram is the hard drive (in particular, ram could disguise itself as the swap partition, to so the OS would treat is as basically a chunk of ram that it would rather not use).

Philip Machanick's RAMpage! (ca. 2000)

> The RAMpage memory hierarchy is an alternative to a conventional cache-based hierarchy, in which the lowest-level cache is managed as a paged memory, and DRAM becomes a paging device.

Re: AMD's Turin: 5th Gen EPYC Launched

#118

Post by KingOfCoders »

aurareturn wrote: post #108

Phoronix recently reviewed the 196 core Turin Dense against the AmpereOne 192 core. * Ampere MSRP $5.5K vs $15K for the EPYC. * Turin 196 had 1.6x better performance * Ampere had 1.2x better energy consumption In terms of actual $/perf, Ampere 192 core is 1.7x better than Turin Dense 196 core based on Phoronix's review. So for $5.5k, you can either buy an AmpereOne 192 core CPU (274w) or a Turin Dense 48 core CPU (30…

The difference is, you can get EPYC CPUs but you can't get hold of Ampere CPUs.

Re: AMD's Turin: 5th Gen EPYC Launched

#119

Post by wmf »

TacticalCoder wrote: post #105

> The system we had access to was running 6000MT/s for its memory, and DDR5-6000 MT/s is what most systems will support in a 1 DIMM per channel configuration. Should you want to run 2 DIMMs per channel, then your memory speeds drop to 4400 MT/s; and if you run 1 DIMM per channel in a motherboard with 2 DIMMs per channel then expect 5200 MT/s for your memory speed. Is this all ECC memory at these speeds?

Yes, servers only use ECC RAM.

Re: AMD's Turin: 5th Gen EPYC Launched

#120

Post by deaddodo »

cubefox wrote: post #107
deaddodo wrote: post #23

Earlier quoted context omitted.

> vid3o g4mes Why do you type it like that?

Old habit. I'm a kid of the 1990s, and we were convinced there wasn't anything cooler than a) video games and b) replacing letters with numbers. It retrospect, we might have been a little biased.

Well, just for future reference; if you're a kid of the 90s, you're well into your 30s now.

It's weird/juvenile to be typing a phrase in a manner similar to a preteen, well after 20+ years have passed. Especially in the middle of an otherwise normal message/conversation.

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