The interactive guide on that page is an effective way to visualise the components in relation to the attacks.
Does anyone know what this would have been built with?
MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
111–118 of 118 posts
Re: MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
#112Earlier quoted context omitted.
Also, HT is not such a great performance win - on a few different 4-core/8-thread machines, I had access to, loading all 8 threads to "100% CPU" (whatever that means) usually only delivers 20-30% faster computation than with HT off (4-core/4-thread) - which is inline with your 30% number. And that's an improvement - some 15 years ago, with similar computational loads, most of my tests ran 10-20% faster with the HT of…
> loading all 8 threads to "100% CPU" (whatever that means) What application?
Lots of numerical computations and simulations.
Re: MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
#113Also for MDS: https://www.intel.com/content/www/us/en/security-center/advi... I like how Intel prominently thanks their own employees for finding the bugs and later simply acknowledges the existence of any anyone independent reporters with zero thanks.
Interesting. This could mean that Intel actually discovered and thus knew about all those security-holes before the non-Intel researchers did.
Or they're just being awkwardly disingenuous here, that's also a possibility.
Re: MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
#114Earlier quoted context omitted.
I think you’re misunderstanding what HT is. It’s not true parallelism, it’s just hiding latency by providing some extra superscalar parallelism. You can’t expect it to give you actual linear improvements in performance because it’s just an illusion.
I understand that very well. But non of the standard tools that manage CPU understand that, and most people don't either. If I had a nickel for every time I had to explain why "You are at 50% CPU now, but you can't actually run twice as many processes on this machine and get the same runtime", I'd be able to buy a large frapuccino or two at starbucks. Perhaps I'm uninformed though - is there a tool like htop, which w…
No there isn’t. But if you understand it I don’t get why you think 20% isn’t a good performance boost, especially considering the rate of return for power and area in silicon.
Re: MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
#115Earlier quoted context omitted.
I understand that very well. But non of the standard tools that manage CPU understand that, and most people don't either. If I had a nickel for every time I had to explain why "You are at 50% CPU now, but you can't actually run twice as many processes on this machine and get the same runtime", I'd be able to buy a large frapuccino or two at starbucks. Perhaps I'm uninformed though - is there a tool like htop, which w…
No there isn’t. But if you understand it I don’t get why you think 20% isn’t a good performance boost, especially considering the rate of return for power and area in silicon.
Because many people believe it is a 100% improvement, plan/budget accordingly, and then look for help.
As far as silicon/power it is nice, but IIRC (I am not involved in purchasing anymore) it used to cost over 50% in USD for those 20% in performance when you non-HT parts were common.
Re: MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
#116Earlier quoted context omitted.
No there isn’t. But if you understand it I don’t get why you think 20% isn’t a good performance boost, especially considering the rate of return for power and area in silicon.
Because many people believe it is a 100% improvement, plan/budget accordingly, and then look for help. As far as silicon/power it is nice, but IIRC (I am not involved in purchasing anymore) it used to cost over 50% in USD for those 20% in performance when you non-HT parts were common.
What a strange way to measure the benefits of a performance optimization: "how people will perceive it and then ask me for help".
Re: MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
#117Earlier quoted context omitted.
Because many people believe it is a 100% improvement, plan/budget accordingly, and then look for help. As far as silicon/power it is nice, but IIRC (I am not involved in purchasing anymore) it used to cost over 50% in USD for those 20% in performance when you non-HT parts were common.
What a strange way to measure the benefits of a performance optimization: "how people will perceive it and then ask me for help".
You ignored the price issue, which was measurable and real, but also:
It (used to be) my job. Does "because people fall for deceptive marketing, waste money, and then waste my time trying to salvage their reputation" sound better?
Re: MDS: Microarchitectural Data Sampling side-channel vulnerabilities in Intel CPUs
#118Earlier quoted context omitted.
According to the researchers in the paper[0] this is not true. >We have verified that we can leak information across arbitrary address spaces and privilege boundaries, even on recent Intel systems with the latest microcode updates and latest Linux kernel with all the Spectre, Meltdown, L1TF default mitigations up (KPTI, PTE inversion, etc.). In particular, the exploits we discuss below exemplify leaks in all the rele…
I searched the the paper and it doesn't seem to falsify what I linked to, but I'll have to dig deeper into the research. "Recent Intel systems" isn't specific enough.
Page 16 in the slides[1] lists vulnerable processors, 8700K is one of them
[1] https://mdsattacks.com/slides/slides.html
edit: This is mentioned in the paper as well, on page 8