Earlier quoted context omitted.
I don't think the RISC-V work is a good example. It suffers from some of the problems that mdwelsh is worried about. It's aimed at a real world problem but their solution is not good. A couple of days ago, someone asked where the verification infrastructure was on https://news.ycombinator.com/item?id=10831601 . So I took another look around and found it was pretty much unchanged from when I looked last time. There is…
That I recall, the RISC-V instruction set was created by looking at existing RISC instructions, industry demands, and so on. The result was a pretty good baseline that was unencumbered by patents or I.P. restrictions. From there, simulators and reference hardware emerged. Unlike many toys, the Rocket CPU was designed and prototyped with a reasonable flow on 45nm and 28nm. Many others followed through with variants fo…
They haven't followed engineering practices which is one of the issues mdwelsh was talking about.
If they've synthesized to 45nm and 28nm, where's all their synthesis stuff - constraints etc.?
They have no back end stuff, very little docs, almost no tests, almost no verification infrastructure.