Earlier quoted context omitted.
HPC admin here, generally serving "long tail of science" researchers. In today's x86_64 hardware, there's no "supercomputer memory subsystem". It's just a glorified NUMA system, and the biggest problem is putting the memory close to your core, i.e. keeping data local in your NUMA node to reduce latencies. Your resource mapping is handled by your scheduler. It knows your hardware, hence it creates a cgroup which satis…
Thanks for the thoughtful comment, pretty fascinating stuff. > In today's x86_64 hardware, there's no "supercomputer memory subsystem". It's just a glorified NUMA system, and the biggest problem is putting the memory close to your core, i.e. keeping data local in your NUMA node to reduce latencies. I mean, memory topology varies greatly by uarch (doubly so between vendors). I can't take a routine tuned to Nehalem, ru…
You're absolutely right, this is why I said that if you're using libraries, this burden is generally handled by them. Also compilers do this and handle this very well.
If you're writing your own routines, the best way is to read the arch docs, maybe some low-level sites like chips and cheese, do some synthetic benchmarks and write your code in a semi informed way.
After writing the code, a suite of cachegrind, callgrind and perf is on order. See if there are any other bottlenecks, and tune your code accordingly. Add hints for your compiler, if possible.
I was able to reach insane saturation levels with Eigen plus, some hand-tuned code. For the next level, I needed to change my matrix ordering, but it was already fast enough (30 minutes to 45 seconds: 40x speedup), so I left it there.
Sometimes there are no replacement for blood, sweat and tears in this thing.
I have never played with custom interconnects (Slingshot, etc.), yet, so I can't tell much.