RISC-V SBC VisionFive 2 Officially Shipped • Hacker News Board

Re: RISC-V SBC VisionFive 2 Officially Shipped

#101

Post by snvzz » Fri, Jan 13, 2023, 7:39 AM UTC

MisterTea wrote: post #98

swetland wrote: post #58

Earlier quoted context omitted.

The CPU itself (Core Complex, including cache, irq controller, etc) is documented by SiFive: https://www.sifive.com/cores/u74-mc Unfortunately there appears to be no detailed documentation at all (unless you count a pile of Linux and bootloader patches, which I don't) for the peripherals, etc, outside of the core complex on the SoC: https://doc-en.rvspace.org/Doc_Center/jh7110.html

> unless you count a pile of Linux and bootloader patches, which I don't This is what drives me crazy. Vendor claims "open source" which means an outdated linux image and the source code is wrapped up inside of a megalith build monstrosity like penguintronix or yocto. Utter junk these things are.

OpenSBI patches are already upstream, and u-boot being reviewed for merging.

It is not anywhere as bad as you're picturing it.

Re: RISC-V SBC VisionFive 2 Officially Shipped

#102

Post by moloch-hai » Fri, Jan 13, 2023, 2:27 PM UTC

zu2_ wrote: post #87

moloch-hai wrote: post #61

Do we know what instruction-set profile it implements? Any?

$ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc

Any clue on Zbb? Zk* and Zbk*?

Can you do regular Linux without S?

Re: RISC-V SBC VisionFive 2 Officially Shipped

#103

Post by MisterTea » Wed, Jan 18, 2023, 12:55 PM UTC

snvzz wrote: post #101

MisterTea wrote: post #98

Earlier quoted context omitted.

> unless you count a pile of Linux and bootloader patches, which I don't This is what drives me crazy. Vendor claims "open source" which means an outdated linux image and the source code is wrapped up inside of a megalith build monstrosity like penguintronix or yocto. Utter junk these things are.

OpenSBI patches are already upstream, and u-boot being reviewed for merging. It is not anywhere as bad as you're picturing it.

> It is not anywhere as bad as you're picturing it.

It is If I want to bootstrap a kernel that isn't Linux.

Re: RISC-V SBC VisionFive 2 Officially Shipped

#104

Post by snvzz » Wed, Jan 18, 2023, 6:17 PM UTC

zu2_ wrote: post #93

snvzz wrote: post #89

Earlier quoted context omitted.

As you say this, I realize I can't find anywhere that it does. I do not know why I thought it did. Possibly as U74-MC[0] supports that option. Interestingly, I also took a look at RVA22[1], and found it requires Zbb but not the whole B. Your /proc/cpuinfo isn't listing Z* extensions. Maybe lscpu output would be more detailed? 0. https://www.sifive.com/cores/u74-mc 1. https://github.com/riscv/riscv-profiles/blob/main/…

Oh, I was mistaken. I've verified that at least the rev instruction works (tested on clang -march=rv64imafdcb0p94).

Got mine.

OpenSBI says:

Boot HART Base ISA : rv64imafdcbx

Re: RISC-V SBC VisionFive 2 Officially Shipped

#105

Post by sacnoradhq » Thu, Jan 19, 2023, 10:53 AM UTC

LargoLasskhyfv wrote: post #92

sacnoradhq wrote: post #54

Earlier quoted context omitted.

Not this board, but a $$ RISC-V from Xilinx's PolarFire does: - Yocto Linux BSP - Buildroot Linux BSP - Embedded Linux from Siemens Embedded - FreeBSD (coming soon) https://www.microchip.com/en-us/products/fpgas-and-plds/syst...

Polarfire FPGAs are not Xilinx! Which means you can't use things like https://f4pga.readthedocs.io ATM, or tools from Xilinx. Instead being chained to whichever proprietary stuff Microchip decides to deliver for dealing with the FPGA-part. I've looked at the board, and don't see the appeal in price, for only mediocre CPU-parts, not enough RAM, altough good enough I/O-options. Makes no sense if you don't want to meddl…

I meant MicroChip. Take a chill pill.