Very nice to see RISC-V growing like that and being in the area of interest by big names such as Google and Intel. Open solutions are critical for risk management but I wonder if desktop/server RISC-V processors are also planned.
The flexibility that makes RISC-V so compelling in embedded roles (what if I want 64 bit address but don't need hardware floating point?) makes it a harder target for the sort of workloads that you'd usually run on a server or desktop. If I were going to create an open high performance core to challenge x86 and ARM's A series cores I'd probably use PowerPC as a base rather than RISC-V. But I do think that RISC-V has…
Other features you're likely to want are also included in the specification, so if you want to write code that uses for example the B bit manipulation extension or the V vector extension (which is scalable with vector width as well, unlike SSE/AVX) you just have to check a standardized 'CPUID' bit and can run your code, and otherwise fall back to other code.
I also believe that the spec may let operating systems hook these instructions and provide fallbacks so application developers don't have to, but I'm not too sure on the specifics of the privileged ISA of RISC-V.