101–110 of 311 posts
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I'm certainly no expert, but I've never been able to run a spinning disk HDD off of a raspberry pi without a powered USB hub. I imagine the thermals and form factor would be hurt pretty badly by including a plausible power supply.
It wouldn't need to be a spinning disk, I'm think SSD or NVME
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Highly unlikely to be very competitive. At this stage it's about getting RISC-V hardware into developers' hands, and previous boards either cost $1000 or were limited in ways where they could not run Linux well. (I am one of the Fedora/RISC-V maintainers.)
Just saw this SiFive board HiFive is retailing for $679, can you please comment if this is any good for toying around ? Specs look more than decent - almost desktop class computing. https://www.crowdsupply.com/sifive/hifive-unmatched
Is there something inherently complicated in adding a SATA/M.2 port to board like this? The RaspberryPi is also "disk-less", which to me is one of the major limitations. It's a super interesting little board, and I love that it's a RISC-V, that could really help getting the CPU in the hands of people. I just don't know enough about these things to understand why there are no storage connectors (other than an SD card…
You can get an SD card with 0.5TB capacity on it for USD$30, what storage needs do you foresee? Also these tend to be used where weight is an issue, so, why do you want to lug around a huge disk?
Is there something inherently complicated in adding a SATA/M.2 port to board like this? The RaspberryPi is also "disk-less", which to me is one of the major limitations. It's a super interesting little board, and I love that it's a RISC-V, that could really help getting the CPU in the hands of people. I just don't know enough about these things to understand why there are no storage connectors (other than an SD card…
FWIW, I believe the IO boards available for the Pi4 CM variants have a PCIe slot that could use used for storage: https://www.raspberrypi.org/products/compute-module-4-io-boa... Lack of sata/m.2 port is very frustrating to me.
The Turing Pi project looks to do that with their next version: https://turingpi.com/v2/
Should be much more stable than a USB3 connection.
Does supporting audio mean that these GPIOs can be used as analog-to-digital converters? There are home automation applications where reading a voltage in an ethernet connected device is a good fit but from what I've seen in a raspberry that requires extra hardware connected to the IO ports.
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> The main difference is that RISC-V is a lot more modular, so it's going to be difficult to distribute binaries for but more flexible if you're doing something completely vertical. Also a lot of the modules have bundle relatively common/easy instructions with niche/difficult ones. E.g. multiply with divide. I don't think it'll be worse than ARM and it's decidedly better than x86. There are SEVEN major revisions of A…
Do you have a reason to think the matrix instructions in the M1 are not those specified in Armv8.6-A?
https://gist.github.com/dougallj/7a75a3be1ec69ca550e7c36dc75...
Can someone explain the technical benefits of this architecture over the competition? That is should I be excited if I don't care about e.g. openness? Or is it simply an effort to create something that is a half-decent cpu alternative but open? Is there anything about RISC-V that is "better" simply because it is a later design than others? Is it likely to evolve faster because it is open or more modern?
I think in the real world "No percentage of each sale payments to ARM" is what will drive RISC-V. An "open" ISA doesn't force anything else to be open. So, use cases like Western Digital, where they can quit paying ARM a percentage of every hard drive they sell, for example. As for technical advantages, each RISCV vendor has their own choice of how to implement, so it's hard to say anything broad that applies to all…
The percentage is very small, though. So this argument only works for very high volume use cases, which is why the RISC-V eval boards are currently far more expensive than comparable ARMs.
Do WD do their own silicon yet, or do they just buy the parts?
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I think in the real world "No percentage of each sale payments to ARM" is what will drive RISC-V. An "open" ISA doesn't force anything else to be open. So, use cases like Western Digital, where they can quit paying ARM a percentage of every hard drive they sell, for example. As for technical advantages, each RISCV vendor has their own choice of how to implement, so it's hard to say anything broad that applies to all…
> quit paying ARM a percentage The percentage is very small, though. So this argument only works for very high volume use cases, which is why the RISC-V eval boards are currently far more expensive than comparable ARMs. Do WD do their own silicon yet, or do they just buy the parts?
"Open source" with nvidia hardware? Good luck with that
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As per the Ars link; > The initial pilot run of BeagleV will use the Vision DSP hardware as a graphics processor, allowing a full graphical desktop environment under Fedora. Following hardware runs will include an unspecified model of Imagine GPU as well.
Also, ImgTec are planning on writing and upstreaming open drivers for Linux and mesa for another RISC-V based board, so probably those drivers will work here too. https://riscv.org/blog/2020/11/picorio-the-raspberry-pi-like...