It's quite an interesting world where AMD has one of the 8 cores on a chip-let be a Xilinx FPGA. The only issue is they are not easy enough to program but maybe AMD can get out ahead of Nvidia on this one and define the software stack here in the way Nvidia did with CUDA.
VHDL / Verilog is very different, but not necessarily harder per-se. It's just people spend 4 years learning "normal" programming, and at best have a one-semester course which uses VHDL. But yes, a software stack would help.
The issue I see is they are slow to compile. I write them daily and it's not that hard to lean when you grok the parallel nature, but generating the HW usually takes at least 10 to 30 mins for a medium sized block, that is a bit of a barrier to entry.
I'm really very bearish on this idea. When Intel bought Altera there were really 3 issues. The first was that they drove growth by bundling their FPGA stuff with their fabrication services - so like someone like Ericson could do half their design on FPGA and then slowly move to ASIC. That was good for Intel because it won them business, but it didn't really do anything for FPGAs. The second thing was bundling FPGAs i…
What do you think of the Xilinx HLS tool, I've only played with examples, but the c code being input looks like regular C, and can generate hardware (though you need pragmas to guide it for max efficiency)
Feels like a datacenter play for specialized compute. Given AMDs domination of server workloads in $/performance, seems like doubling down on that advantage. FPGA is already used today to offload SSL termination from the CPU.
VHDL / Verilog is very different, but not necessarily harder per-se. It's just people spend 4 years learning "normal" programming, and at best have a one-semester course which uses VHDL. But yes, a software stack would help.
As an FPGA dev, I tend to think of HDLs akin to HTML than “code”. It’s just a DSL to describe a graph. Actually pretty similar to how tensorflow is designed.
Yes would expect units of execution and different types of signal processing to come a pre-built blobs.
Totally agree. Being involved with FPGAs for 20+ years now, and Xilinx for the most part of it, I have witnessed the progressive decay of their software quality. The legacy Xilinx tools (Foundation) were far from perfect but at least useable -- and hackable to a degree if you needed to implement workarounds. Those were many times even suggested by Xilinx own employees that were easy to approach and responsive back in…
Vivado is amazing. TCL is chosen because its portable across almost All EDA tools, so by using it, Xilinx are ensuring your existing HW design skills apply to FPGA tools also, instead of the proprietary interfaces ISE used. So while TCL is not a language I like, it is the HW standard so it must be in any serious EDA tool. I use many EDA tools daily (design compiler, primetime, icc2, vcs, xcelium, verdi, redhawk, and…
I'm not sure about amazing (there's certainly worse FPGA tools though), but I think you're right on TCL. It's still a perfectly servicable language to do the job and it's ubiquitous in the industry so you'd need a pretty strong reason to break from it. The terribleness of the tooling comes from other sources (mainly its sheer opaqueness, followed by bugginess, followed and excacerbated by its slowness, though the last point may be hard to get around: place-and-route is not like compiler optimisation, compiler optimisation is almost entirely local decisions, wheras place and route is essentially a global optimisation problem).
There's the possibility of a Xilinx Zynq with AMD x86 cores instead of the ARM cores in current Zynq versions, though I'm not sure that would really be interesting to anyone. Beyond that, there's been research in the past that envisions using a FPGA fabric as an execution unit within the CPU itself: https://www.microsoft.com/en-us/research/project/emips/ Intel hasn't pursued such a thing but that doesn't mean AMD cou…
I think you'd have a hard time making a large FPGA actually part of a CPU die due to area. A peer on the memory bus ala CCIX on the other hand... Have you ever thought of building your own processor or maybe just defining your own machine instructions? With eMIPS now you can. Microcode strikes me as the natural way to define arbitrary instructions.
I'm not so sure that's something which is really feasible from a design point of view. Everything involving instructions in the CPU is extremely performance critical and cross-cutting, so designing an interface which allows custom instructions without utterly destroying performance seems like quite a feat. I've a feeling the memory interface is a much more natural place for any integration (this is how it works on any existing FPGA + CPU chips)
Agreed, altera looks dead since intel took over. This is probably good news only for Lattice Semiconductor.
When Jim Anderson left AMD to take on CEO at Lattice I invested heavily in them with the thesis that there would be an eventually merger. Unsure what to do now
With microsemi doing everything wrong, altera going invisible and xilinx soom to becomes AMDs toy project, who else should you invest in?
Vivado is amazing. TCL is chosen because its portable across almost All EDA tools, so by using it, Xilinx are ensuring your existing HW design skills apply to FPGA tools also, instead of the proprietary interfaces ISE used. So while TCL is not a language I like, it is the HW standard so it must be in any serious EDA tool. I use many EDA tools daily (design compiler, primetime, icc2, vcs, xcelium, verdi, redhawk, and…
I'm not sure about amazing (there's certainly worse FPGA tools though), but I think you're right on TCL. It's still a perfectly servicable language to do the job and it's ubiquitous in the industry so you'd need a pretty strong reason to break from it. The terribleness of the tooling comes from other sources (mainly its sheer opaqueness, followed by bugginess, followed and excacerbated by its slowness, though the las…
I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design compiler was designed in the 90s, and while it has many advanced features, it's usability is incredibly poor. A million variables you never heard of, and each one tweaks its behaviour in weird and wonderful ways, and a GUI that still looks like its from the 90s. Costs 90k a seat to boot, but if you're doing ASIC design, it's one of the major tools you will use. And it just does the synthesis bit. Vivado does it all, and has seamless cross probing between each stage, right back to source code. It's usability to me is refreshing. I have found bugs, sure, but never a show stopper. It's free Verilog simulator (xsim) is better than any other free system Verilog simulator out there, and that's just one sub component of Vivado.
When Jim Anderson left AMD to take on CEO at Lattice I invested heavily in them with the thesis that there would be an eventually merger. Unsure what to do now
With microsemi doing everything wrong, altera going invisible and xilinx soom to becomes AMDs toy project, who else should you invest in?
I'm curious what you mean about Microsemi doing everything wrong? I've been pretty happy with my experience with the Polarfire line so far.
I'm not sure about amazing (there's certainly worse FPGA tools though), but I think you're right on TCL. It's still a perfectly servicable language to do the job and it's ubiquitous in the industry so you'd need a pretty strong reason to break from it. The terribleness of the tooling comes from other sources (mainly its sheer opaqueness, followed by bugginess, followed and excacerbated by its slowness, though the las…
I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design compiler was designed in the 90s, and while it has many advanced features, it's usability is incredibly poor. A million variables you never heard of, and each one tweaks its behaviour in weird and wonderful ways, and a GUI that still looks like its from the 90s.…
oh yeah, by all accounts ASIC design tools are even worse. But from a software perspective FPGA tooling is still in the dark ages from most perspectives (and the frustrating thing is a lot of it wouldn't be very hard to do better).