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[1] http://www8.hp.com/hpnext/posts/discover-day-two-future-now-...
Is verilog design small enough to put on an FPGA?
I'd really like to see the full ISA, etc for the chip. A few years ago, I was doing research on building a byte code based vm after working through Peter Michaux "Scheme From Scratch" http://peter.michaux.ca/articles/scheme-from-scratch-introdu... . (I highly recommend running through his code, but do the GC earlier, it's easier to get it from the start than to try to add it.) I couldn't find anything online listing…
There are a few PDFs with the original Lisp Machine ISA, if I am not mistaken. I will have a look when back at home.
There's significantly more for the TI Explorer Lisp machine: http://bitsavers.trailing-edge.com/pdf/ti/explorer/
And even more for Symbolics: http://bitsavers.trailing-edge.com/pdf/symbolics/
Xerox did a Lisp machine line: http://bitsavers.trailing-edge.com/pdf/xerox/interlisp/
There's a working emulator for the MIT CADR: http://www.unlambda.com/cadr/index.html
And you can of course run Genera in an emulator: http://www.unlambda.com/download/genera/
There's a semi working TI explorer emu: http://www.unlambda.com/lispm/
I'd really like to see the full ISA, etc for the chip. A few years ago, I was doing research on building a byte code based vm after working through Peter Michaux "Scheme From Scratch" http://peter.michaux.ca/articles/scheme-from-scratch-introdu... . (I highly recommend running through his code, but do the GC earlier, it's easier to get it from the start than to try to add it.) I couldn't find anything online listing…
There are a few PDFs with the original Lisp Machine ISA, if I am not mistaken. I will have a look when back at home.
Earlier quoted context omitted.
There are a few PDFs with the original Lisp Machine ISA, if I am not mistaken. I will have a look when back at home.
If you mean the LMI Lisp machine: http://bitsavers.trailing-edge.com/pdf/lmi/ There's significantly more for the TI Explorer Lisp machine: http://bitsavers.trailing-edge.com/pdf/ti/explorer/ And even more for Symbolics: http://bitsavers.trailing-edge.com/pdf/symbolics/ Xerox did a Lisp machine line: http://bitsavers.trailing-edge.com/pdf/xerox/interlisp/ There's a working emulator for the MIT CADR: http://www.unlambd…
There is a working TI explorer emulator: http://www.unlambda.com/index.php?n=Main.Meroko
An updated version of the MIT CADR emulator: http://trac.common-lisp.net/mit-cadr/browser/
Source trees for the LMI and TI machines are also on the web.
No links to the actual thing?
http://www.mail-archive.com/picolisp@software-lab.de/msg0483...
...But still no links to source. (As I understand it, this hardware design is expressed in the form of verilog source code.)
Earlier quoted context omitted.
There are a few PDFs with the original Lisp Machine ISA, if I am not mistaken. I will have a look when back at home.
If you mean the LMI Lisp machine: http://bitsavers.trailing-edge.com/pdf/lmi/ There's significantly more for the TI Explorer Lisp machine: http://bitsavers.trailing-edge.com/pdf/ti/explorer/ And even more for Symbolics: http://bitsavers.trailing-edge.com/pdf/symbolics/ Xerox did a Lisp machine line: http://bitsavers.trailing-edge.com/pdf/xerox/interlisp/ There's a working emulator for the MIT CADR: http://www.unlambd…
Is verilog design small enough to put on an FPGA?
FPGAs are the only context in which I've ever encountered Verilog, so I'm gonna say yes?
For simulation, you compile verilog with a software tool into something executable by a VM or natively. This is heavily event based in execution, with events being edge transitions (a signal going from 0->1 or 1->0) occuring at specific times--for most (but not all) cases.
For producing something usable by an FPGA or a foundry for an ASIC, instead of compiling you synthesize. Different tool. Synthesis is the process of taking higher level hardware descriptions and outputing the lower level descriptions usually called a netlist. It's akin to translating C into assembly for example.
Device specific tools can take that netlist and create a bitstream for configuring an FPGA, or the foundry can take that netlist and go through a process called "physical synthesis" which takes the netlist and chooses from the foundry's library the components that will work best for that netlist to operate at speed, figure out where to place them on the die, and insert buffers as needed.
What the GP was asking: is this design small enough to fit in an FPGA. This question is orthogonal to the language used to describe the hardware.
I'd say they answer is yes, depending on the FPGA you choose. Some FPGAs are pretty high capacity these days, and even fast.