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LowRISC: Open-source RISC-V SoC

lowrisc.org

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Re: LowRISC: Open-source RISC-V SoC

#11

Post by ajross »

Hm... the link only talks about the CPU, but calls itself a SoC. There's a lot more than needs to go on any chip that calls itself a "SoC", and much of it is very poorly served by existing "open source" solutions:

    + DRAM
    + I2C
    + GPIO (with stuff like 3.3v, tristate outputs, pull up/down, etc...)
    + USB2 host/device
    + SD/MMC
And that's just at the very basic level. Once you get into the consumer world you need to start talking about video output, camera input, video decode and encode acceleration, programmable GPUs,...

Really the CPU is, in some sense, the most solved problem from the perspective of open source. The designs themselves may be closed IP, but the instruction sets are meticulously documented and their behavior is very standard across many vendors and ISAs.

Re: LowRISC: Open-source RISC-V SoC

#12

Post by mjn »

makomk wrote: post #8
cottonseed wrote: post #3

I'm not familiar with the IP issues. Would it be possible to center open-source processor development around the ARM instruction set? It looks like the privileged part of the RISC-V ISA is not finished yet. This is a great project, but it seems a long way off.

I'm surprised they don't just use OpenRISC, there's already hardware shipping that uses ASIC implementations of that internally.

They discuss their reasoning briefly in the manual [1, p. 3]:

We are far from the fi rst to contemplate an open ISA design suitable for hardware implementation. We also considered other existing open ISA designs, of which the closest to our goals was the OpenRISC architecture. We decided against adopting the OpenRISC ISA for several technical reasons:

-- OpenRISC has condition codes and branch delay slots, which complicate higher performance implementations.

-- OpenRISC uses a fixed 32-bit encoding and 16-bit immediates, which precludes a denser instruction encoding and limits space for later expansion of the ISA.

-- OpenRISC does not support the 2008 revision to the IEEE 754 floating-point standard.

-- The OpenRISC 64-bit design had not been completed when we began.

[1] http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54...

Re: LowRISC: Open-source RISC-V SoC

#13

Post by userbinator »

RISC-V looks like MIPS but with some of the more dubious design decisions of the time (e.g. branch delay slots) fixed. The mix of 16-bit and 32-bit instruction lengths is reminiscent of ARC.

In other words, the characteristics of SoCs using this core will likely be very similar to the many out there using MIPS: cheap and simple, with performance that's acceptable for applications like routers and other embedded devices.

Re: LowRISC: Open-source RISC-V SoC

#14

Post by nullc »

ajross wrote: post #11

Hm... the link only talks about the CPU, but calls itself a SoC. There's a lot more than needs to go on any chip that calls itself a "SoC", and much of it is very poorly served by existing "open source" solutions: + DRAM + I2C + GPIO (with stuff like 3.3v, tristate outputs, pull up/down, etc...) + USB2 host/device + SD/MMC And that's just at the very basic level. Once you get into the consumer world you need to start…

Greetings. I use some of those aforementioned very standard CPUs and have an issue: Many tasks I use the computer for are far more security critical than performance critical I would like have someone augment a cpu design that I'm using to give it 256 bit 'pointers' which pack 64 bit start, end, and offset, and a set of fine grained permissions and special privileged instructions for modifying these pointers. This way huge classes of security vulnerabilities will be prevented by the hardware.

I won't mind if it's 10x slower— though the thousands of times slower that I'd get with a software simulation would likely be too slow to be practical.

What? You say that the chips I currently used have closed and secret designs and are not available for modification? But I thought you said that the CPU is the most solved problem from the perspective of open source??

I guess it's good that people are working on actually open CPUs so that things like http://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ can be built.

Re: LowRISC: Open-source RISC-V SoC

#15

Post by delinka »

nullc wrote: post #14
ajross wrote: post #11

Hm... the link only talks about the CPU, but calls itself a SoC. There's a lot more than needs to go on any chip that calls itself a "SoC", and much of it is very poorly served by existing "open source" solutions: + DRAM + I2C + GPIO (with stuff like 3.3v, tristate outputs, pull up/down, etc...) + USB2 host/device + SD/MMC And that's just at the very basic level. Once you get into the consumer world you need to start…

Greetings. I use some of those aforementioned very standard CPUs and have an issue: Many tasks I use the computer for are far more security critical than performance critical I would like have someone augment a cpu design that I'm using to give it 256 bit 'pointers' which pack 64 bit start, end, and offset, and a set of fine grained permissions and special privileged instructions for modifying these pointers. This wa…

And with an "actually open CPU," how does one verify that the silicon in the final package is actually what's in the design and that no "closed and secret designs" have been added by the fabricator?

Re: LowRISC: Open-source RISC-V SoC

#17

Post by sitkack »

higherpurpose wrote: post #7
wmf wrote: post #4

Earlier quoted context omitted.

Historically, ARM really, really did not like unlicensed or open-source ARM processors. But times change, so I wouldn't be surprised to see them take some easy PR from openwashing at some point.

That seems highly unlikely - unless we're talking about 3rd generation behind the latest tech chips. I could see them open source say the ARMv6 architecture in 3+ years, when ARMv8 has already taken off, and ARMv7 is in legacy mode. But meh.

ARM would very aggressively go after any open source implementation of the ARM ISA. For the longest time you couldn't find any ARM documentation on the net because it was all behind a license agreement that read, "won't be used to make an open source version of our schwag"

Re: LowRISC: Open-source RISC-V SoC

#18

Post by sitkack »

userbinator wrote: post #13

RISC-V looks like MIPS but with some of the more dubious design decisions of the time (e.g. branch delay slots) fixed. The mix of 16-bit and 32-bit instruction lengths is reminiscent of ARC. In other words, the characteristics of SoCs using this core will likely be very similar to the many out there using MIPS: cheap and simple, with performance that's acceptable for applications like routers and other embedded devic…

I would attempt a nibble based compact instruction representation to reduce external memory bandwidth. Fixed width instructions kinda suck now that memory is such a bottleneck.

Re: LowRISC: Open-source RISC-V SoC

#19

Post by sitkack »

delinka wrote: post #15
nullc wrote: post #14

Earlier quoted context omitted.

Greetings. I use some of those aforementioned very standard CPUs and have an issue: Many tasks I use the computer for are far more security critical than performance critical I would like have someone augment a cpu design that I'm using to give it 256 bit 'pointers' which pack 64 bit start, end, and offset, and a set of fine grained permissions and special privileged instructions for modifying these pointers. This wa…

And with an "actually open CPU," how does one verify that the silicon in the final package is actually what's in the design and that no "closed and secret designs" have been added by the fabricator?

You need to xray the die and confirm the designs are the same, but it doesn't guarantee that extra or bad transistors aren't inserted that leak data.

You never really know.

https://www.cl.cam.ac.uk/~sps32/ches2012-backdoor.pdf

https://www.usenix.org/legacy/event/leet08/tech/full_papers/...

http://en.wikipedia.org/wiki/Hardware_Trojan

Re: LowRISC: Open-source RISC-V SoC

#20

Post by jontaylor »

alain94040 wrote: post #2

Volume silicon manufacture is planned I highly doubt it. But if it's true, that would be the missing link for all open source hardware design. It would also be nice if they gave some idea of the kind of performance or implementation they are considering.

So you would say this isn't a low risc proposition?
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