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MyHDL – Design hardware with Python – Examples

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Re: MyHDL – Design hardware with Python – Examples

#11

Post by wyager »

hrjet wrote: post #10
wyager wrote: post #6

There is so much potential in open source hardware design. Right now, we are held back by (at best) mediocre tools. We need better HDL software, better synthesis software, better EDA software before we have any hope of widespread use of open source hardware. Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. Open source soft…

I think this is where FPGAs might prove very useful. Even if the designs made on FPGAs are small-scale, amateurish or sub-optimal today, they will help develop an ecosystem of tools, including open-source tools, that will ultimately help larger-scale open-source hardware.

The problem with FPGAs is the design software. Have you ever tried to use WebPACK ISE or Quartus? Both of them blow. Terrible UI, terrible design, terrible licensing requirements.

We need simple, easy, powerful, and free tools for FPGA development before open source FPGA cores take off.

Re: MyHDL – Design hardware with Python – Examples

#12

Post by hrjet »

wyager wrote: post #11
hrjet wrote: post #10

Earlier quoted context omitted.

I think this is where FPGAs might prove very useful. Even if the designs made on FPGAs are small-scale, amateurish or sub-optimal today, they will help develop an ecosystem of tools, including open-source tools, that will ultimately help larger-scale open-source hardware.

The problem with FPGAs is the design software. Have you ever tried to use WebPACK ISE or Quartus? Both of them blow. Terrible UI, terrible design, terrible licensing requirements. We need simple, easy, powerful, and free tools for FPGA development before open source FPGA cores take off.

I am agreeing with your first point.

But I am suggesting an alternative to your second point. When FPGA boards become available to more people, the tools will automatically come. Note that, the open-source tools can be built by software professionals, even though they might be amateurs in hardware design.

Re: MyHDL – Design hardware with Python – Examples

#15

Post by phaemon »

wyager wrote: post #6

There is so much potential in open source hardware design. Right now, we are held back by (at best) mediocre tools. We need better HDL software, better synthesis software, better EDA software before we have any hope of widespread use of open source hardware. Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. Open source soft…

> Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit.

That's pretty much what we did have, before RMS started GCC. I guess we need an RMS for hardware!

Re: MyHDL – Design hardware with Python – Examples

#16

Post by simias »

DanWaterworth wrote: post #8

I've recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here's a snippet of how it looks so far (though things are changing rapidly): lt : BoolO…

That's just combinational logic, how do you implement clocked processes and latches?

In my (admittedly limited) experience with hardware design making correct pure combinational logic isn't generally too difficult, it's keeping track of the state and state transitions that's problematic.

Re: MyHDL – Design hardware with Python – Examples

#17

Post by noselasd »

hrjet wrote: post #12
wyager wrote: post #11

Earlier quoted context omitted.

The problem with FPGAs is the design software. Have you ever tried to use WebPACK ISE or Quartus? Both of them blow. Terrible UI, terrible design, terrible licensing requirements. We need simple, easy, powerful, and free tools for FPGA development before open source FPGA cores take off.

I am agreeing with your first point. But I am suggesting an alternative to your second point. When FPGA boards become available to more people, the tools will automatically come. Note that, the open-source tools can be built by software professionals, even though they might be amateurs in hardware design.

Thee's already cheap ($50 and less) FPGA boards. But all FPGAs are proprietary, there's no available documentation on the internals, the bitstream, and many other things one need to create 3.party/open source tools.

And I also suspect they're hard to impossible to reverse engineer.

Re: MyHDL – Design hardware with Python – Examples

#18

Post by DanWaterworth »

simias wrote: post #16
DanWaterworth wrote: post #8

I've recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here's a snippet of how it looks so far (though things are changing rapidly): lt : BoolO…

That's just combinational logic, how do you implement clocked processes and latches? In my (admittedly limited) experience with hardware design making correct pure combinational logic isn't generally too difficult, it's keeping track of the state and state transitions that's problematic.

I'm glad you asked. At the moment, only combinational circuits are possible, but I'm working to extend this to synchronous (clocked) circuits.

When you need feedback, there will be a combinator that will look something like this:

    feedback : Vect n Bool -> (Vect i v -> Vect n v -> SSA op v (Vect n v, Vect o v)) -> Vect i v -> SSA op v (Vect o v)
This is all up in the air. I'm still working it through.

I'm very keen to end up with something that it nice to use, even at the expense of being difficult to implement.

I may be getting ahead of myself, but I'd like to have functions that do things like: take a combinational circuit and return a synchronous circuit where the logic is evenly separated (in terms of delay) over n clock cycles.

Re: MyHDL – Design hardware with Python – Examples

#19

Post by DanWaterworth »

noselasd wrote: post #17
hrjet wrote: post #12

Earlier quoted context omitted.

I am agreeing with your first point. But I am suggesting an alternative to your second point. When FPGA boards become available to more people, the tools will automatically come. Note that, the open-source tools can be built by software professionals, even though they might be amateurs in hardware design.

Thee's already cheap ($50 and less) FPGA boards. But all FPGAs are proprietary, there's no available documentation on the internals, the bitstream, and many other things one need to create 3.party/open source tools. And I also suspect they're hard to impossible to reverse engineer.

Here's one attempt: https://github.com/Wolfgang-Spraul/fpgatools
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