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Book: RISC-V System-on-Chip Design

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Re: Book: RISC-V System-on-Chip Design

#11

Post by rwmj »

timhh wrote: post #9
sylware wrote: post #7

Everything RISC-V is good (even the mistakes which is making it more robust and more mature).

I like RISC-V (it's been my job for the last 7 years) but this is nonsense. Not everything RISC-V is good. CLIC was awful (thankfully it has been abandoned). The spec is not especially well written - the style is inconsistent due to being written by many authors, and it is waaaay too much of a textbook rather than a proper spec. (There is some ongoing work to improve this tbf.) There's a practically unending list of…

I broadly agree with your points except one.

Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C. There's no practical way for such binaries to detect this and work around it at runtime as they can with other extensions. And emulation would be super-slow given a large proportion of instructions are compressed.

Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it. Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.

Also interested in the problems you see in Zicond. It claims at least to give you most of the benefit of conditional moves using only two instructions, but I've not actually tried using it. (https://docs.riscv.org/reference/isa/extensions/zicond/_atta...)

Re: Book: RISC-V System-on-Chip Design

#16

Post by dmpk2k »

dmpk2k wrote: post #6
colinb wrote: post #2

Ooof. €109.70 in paperback

You can get it direct from Elsevier for ~78 euros: https://shop.elsevier.com/books/risc-v-system-on-chip-design...

Maybe it's just a regional thing, but it's showing 78 euros for the paperback for me. Plus I bought the paperback recently at that price too.

Re: Book: RISC-V System-on-Chip Design

#17

Post by Joker_vD »

rwmj wrote: post #11
timhh wrote: post #9

Earlier quoted context omitted.

I like RISC-V (it's been my job for the last 7 years) but this is nonsense. Not everything RISC-V is good. CLIC was awful (thankfully it has been abandoned). The spec is not especially well written - the style is inconsistent due to being written by many authors, and it is waaaay too much of a textbook rather than a proper spec. (There is some ongoing work to improve this tbf.) There's a practically unending list of…

I broadly agree with your points except one. Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C. There's no practical way for such binaries to detect this and work around it at runtime as they can with other extensions. And emulation would be super-slow given a large proportion of instructions are compressed. Also the excus…

> RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it.

...no, not really? There is nothing like 9 byte-long MOVABS instruction of x64 that exists on RISC-V.

The main difficulty in decoding is that 32-bit instructions are not required to be 4-byte aligned, this means that naïve decoders will spend 2 cycles fetching such split instructions. It's possible to add a 4-byte ring buffer but all in all, efficiently supporting the C extension is non-trivial.

Re: Book: RISC-V System-on-Chip Design

#18

Post by genxy »

Excellent find, an academic paper announcing the book is here

https://peer.asee.org/57147.pdf

Harris and Harris (no relation) have an excellent book on digital design using RISC-V as the domain problem, https://pages.hmc.edu/harris/ddca/ddcarv.html

https://pages.hmc.edu/harris/ddca/

Their books are perfect, and I hope this textbook gets adopted by thousands of colleges. Our RISC-V future is bright, now we need one on SoC bringup and getting your OS running on that SoC.

Re: Book: RISC-V System-on-Chip Design

#19

Post by rwmj »

Joker_vD wrote: post #17
rwmj wrote: post #11

Earlier quoted context omitted.

I broadly agree with your points except one. Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C. There's no practical way for such binaries to detect this and work around it at runtime as they can with other extensions. And emulation would be super-slow given a large proportion of instructions are compressed. Also the excus…

> RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it. ...no, not really? There is nothing like 9 byte-long MOVABS instruction of x64 that exists on RISC-V. The main difficulty in decoding is that 32-bit instructions are not required to be 4-byte aligned, this means that naïve decoders will spend 2 cycles fetching such split instructions. It's possible to a…

RISC-V definitely does support instructions longer than 32 bits, starting at 48 bits (ie. 32 + 16), and going much longer. They are much easier to decode than x86 because the length is evident from the first byte. No ratified extension uses them now, but you're going to need to deal with them as the extension space gets more crowded. Including dealing with instructions split across cache lines and pages, and instructions aligned to 16 bits.

I'm not sure what point you're making TBH.

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