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How far away are we from being able to run a hobby Linux on something like that, a completely hardware-backdoor-free system?
Aegis – open-source FPGA silicon
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Re: Aegis – open-source FPGA silicon
#12We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M...
The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips.
In the case of Morphle Logic we make wafer scale integrations (WSI) with 10 billion transistors at 180nm for $750. That yields around 300 million 'gates', the largest commercial FPGA's barely get to 3 million. So our Morphle Logic WSI is the largest and fastest (up to 12 Ghz) FPGA you could get if we can find a few hundred buyers who want to pay up front (crowdfunding). Please email me if you are interested in such a enormous fast FPGA.
I'll buy an Aegis FPGFA test chip just to find out how hard it is to test a test chip.
Good luck RossComputerGuy, I hope you get working chips back. The same fab and supplier lost our first taped-out chips in the mail... and then they went bankrupt.
Re: Aegis – open-source FPGA silicon
#13Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work. But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix. I know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work fo…
You can come work with us/for us and scale your SerDes design for us. That gets you actual wafer mask sets taped-out, a million chips and a WSI, not just test chips. A succesful SerDes will get you a job (at least in Europe).
How fast will the SerDes run, 50 Mhz? It is not clear to me from the serdes_tile.dart source code. Can you share the verilog files?
Re: Aegis – open-source FPGA silicon
#14Re: Aegis – open-source FPGA silicon
#15Excellent. Put me down for a couple.
me too please
Re: Aegis – open-source FPGA silicon
#16[dead]
How do you verify that the fab produces the design authentically? They could create a security vulnerability only they know how to exploit.
Re: Aegis – open-source FPGA silicon
#17[dead]
How do you verify that the fab produces the design authentically? They could create a security vulnerability only they know how to exploit.
That’s a nice theory. Fab is one thing, but there are afterwards packaging and testing facilities where silicon can be swapped. I worked for a short time for a military contractor. They don’t X-ray every single chip. They just use it assuming the ordered chip is the one which was delivered by the markings on the package.
Re: Aegis – open-source FPGA silicon
#18Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
Re: Aegis – open-source FPGA silicon
#19[dead]
How do you verify that the fab produces the design authentically? They could create a security vulnerability only they know how to exploit.
X-ray would be the traditional approach, though quite expensive.
IRIS by bunnie is another approach that aims to bring cost way down. Ref https://www.bunniestudios.com/blog/2024/iris-infra-red-in-si...