Sequential Optimal Packing for PCB Placement • Hacker News Board

Re: Sequential Optimal Packing for PCB Placement

#11

Post by rcxdude » Sat, Apr 04, 2026, 4:34 PM UTC

summa_tech wrote: post #7

rcxdude wrote: post #6

Earlier quoted context omitted.

I do think autorouting is largely a UI problem for this reason. Specifying the constraints is very difficult, especially when it's also tied into assessing stuff like power distribution (where the rule of thumb of 100nF is almost certainly suboptimal, proximity probably matters less than you would think, and you can wind up with too much capacitance, but actually evaluating what matters is so much more complex that u…

For the traditional "100 nF per pin" problem, there is an actual constraint based solution. What you _really_ want is an impedance and cross-impedance constraint on current loops through power pins. That's, ultimately, what matters: not some rule of thumb, but actual physics that attempts to quantify the board's response to the chip's changing load. Interestingly, Qualcomm actually gives you these, but I haven't seen…

Yeah, you can do it, but it's quite a painful process and as you noted it's quite hard to actually get the required information: you can predict the impedance at the chip's pads across frequency, but only with a full-fledged simulation of the PCB, and then you don't actually know what counts as good enough in most cases. What I'd like is something that's a little easier to analyse and visualise even if a little less precise. It feels like there should be a much simpler model which gives you a view of how the impedance changes as you move away from the capacitor so that you can evaluate the tradeoffs without needing to set up and wait for a whole simulation.

(especially because as I understand it, distance tends to matter a lot less than people expect, especially because once you're up at frequencies where it might matter, it's not so much the capacitors providing the decoupling as the power planes themselves anyhow)

Re: Sequential Optimal Packing for PCB Placement

#12

Post by estimator7292 » Sat, Apr 04, 2026, 8:50 PM UTC

crote wrote: post #3

The problem is that PCB design is hard . Writing a "cost function" for placement is basically impossible when later design steps are going to introduce hard constraints, and earlier design steps are actually extremely flexible. For example, the general rule-of-thumb is to place one 100nF decoupling capacitor per power pin. But in practice there isn't always space for that. Do you suboptimally route your critical high…

Exactly. Packing components isn't the problem. Routing traces isn't the problem. Both of those can be accomplished with fairly straightforward algorithms. We've had auto-placing and auto-routing for decades, and they serve their purposes well enough.

The hard part is that 98% of laying out a PCB has nothing to do with laying out a PCB. The hard part is analyzing and predicting how every individual trace or component interacts with literally all other traces and components at once. You have to track and model current paths, ground and power plane inductance. You have to just know what parts of the circuit are critical and which traces to keep away from others. Almost all of the work involved in producing a PCB is in designing and understanding the circuit and the physical implications of each and every section, wire, and component.

Routing a PCB is easy. Engineering a correct PCB is not, and there's a lot more involved than drawing traces between pins.

I find it actually pretty confusing that people are still trying to automate the naive approach to PCB design. If your circuit is simple enough to not care about the finer details, traditional algorithms are all you need. For anything more complex, placement and routing just aren't the primary problem, and you can't solve the real underlying challenges by solving placement and routing.

I don't think these problems are inherently un-computable, but they are very hard problems that take humans many years of training and experience to work through. I think they are likely beyond our reach for the moment.

Re: Sequential Optimal Packing for PCB Placement

#13

Post by crote » Sat, Apr 04, 2026, 10:46 PM UTC

estimator7292 wrote: post #12

crote wrote: post #3

The problem is that PCB design is hard . Writing a "cost function" for placement is basically impossible when later design steps are going to introduce hard constraints, and earlier design steps are actually extremely flexible. For example, the general rule-of-thumb is to place one 100nF decoupling capacitor per power pin. But in practice there isn't always space for that. Do you suboptimally route your critical high…

Exactly. Packing components isn't the problem. Routing traces isn't the problem. Both of those can be accomplished with fairly straightforward algorithms. We've had auto-placing and auto-routing for decades, and they serve their purposes well enough. The hard part is that 98% of laying out a PCB has nothing to do with laying out a PCB. The hard part is analyzing and predicting how every individual trace or component…

> Packing components isn't the problem. Routing traces isn't the problem. Both of those can be accomplished with fairly straightforward algorithms. We've had auto-placing and auto-routing for decades, and they serve their purposes well enough.

I have to disagree. Even small subsections of, say, routing are already NP-hard. In my experience autorouters are universally awful: they fall apart as soon as you feed them anything which isn't completely trivial. The problem is just too complicated to solve with a bunch of heuristics and clever approximations.

Re: Sequential Optimal Packing for PCB Placement

#14

Post by edg5000 » Sun, Apr 12, 2026, 4:50 AM UTC

bestouff wrote: post #5

edg5000 wrote: post #4

I think using the vision decoder baked into modern LLMs is the way to go. Have the LLM iterate; make sure it can assert placement qualities and understands the hard requirements. I think it can be done.

I tried having Opus 4.6 route a PCB for me last month. The result was afwul. I'd be interested if there was a working solution to this.

They do a have a vision decoder like many other LLMs, so in theory it should be able to write the positions textually, then call a render command, then look at the rendered bitmap. I's all very opaque though; I'd love a visualisation of the latent space data that it's converting the image to. I found that very long vertical images throw Opus off completetely for example. It's very interesting to experiment with this. Let it play with placement and let it call a render command. Then let is describe in detail what it sees. I'll be looking into this a lot this year. Maybe there will be niche models that will be smaller but have better vision capabilities then Opus. A world where one model rules would be incredibly depressing (kinda like what we saw with some software companies since the 90s).