11–20 of 84 posts
Very cool! So there’s 5x riscV cores available?
Yes, 1x Vexriscv RV32-IMAC + MMU, and 4x PicoRV32's as RV32E-MC for I/O processing, configured with extensions to enable deterministic, real-time bit-banging without having to count clocks.
> Those with a bit of silicon savvy would note that it’s not cheap to produce such a chip, yet, I have not raised a dollar of venture capital. I’m also not independently wealthy. So how is this possible? What kind of order of magnitude of cost are we talking about? What are the next steps - is there some service to cut the wafer and put into a package for you?
After coming out of the fab, the chips go through probing, packaging and reeling.
This is about transparency just like the Precursor, right? How can I know that my Baochip-1x is really what it says it is?
Thanks man!
Earlier quoted context omitted.
Yes, 1x Vexriscv RV32-IMAC + MMU, and 4x PicoRV32's as RV32E-MC for I/O processing, configured with extensions to enable deterministic, real-time bit-banging without having to count clocks.
That reminds me a lot of the xmos xcore mcus with 8 cores. I am curious what kind of synchronization primitives have you added and why?
Earlier quoted context omitted.
That reminds me a lot of the xmos xcore mcus with 8 cores. I am curious what kind of synchronization primitives have you added and why?
I'm actually working on a comprehensive write up on exactly this topic that should be out sometime next week!
Is there a way to bootstrap binary code into the reram? I’m thinking being able to ‘hand-type’ in a few hundred byte kernel rather than use a flashing tool
I didn't know there were partially open source RISC-V. I might have missed it in the article, but what was the reason for having some parts closed source?