[flagged]
It's basically a transcript of a conversation, so obviously it's not going to read as edited prose.
Interviewing Intel's Chief Architect of x86 Cores
11–20 of 29 posts
Re: Interviewing Intel's Chief Architect of x86 Cores
#12Earlier quoted context omitted.
Because that costs power and area.
And it still does. And the last generation was wider and deeper than the one before it, also costing power and area. The question that should be asked ... but which would never be answered ... is "What was it that you changed that REQUIRED and ALLOWED you to go wider and deeper?" It's not a new process node every time. Theres no NEED to have a massive reorder buffer unless you can decode and dispatch that number of i…
Re: Interviewing Intel's Chief Architect of x86 Cores
#13Oh em gee ... what a contentless interview. "We made it wider and deeper". Gosh. Why didn't anyone think about doing that before?
I asked chatgpt to give a contentful summary of the interview, it seems to be more or less accurate, albeit surface level. If anyone is interested.
It gets the "why" but not the "how". Maybe someone here can prompt it further to speculate on the "how". I don't think I'll be able to verify its output well enough to do that.
Re: Interviewing Intel's Chief Architect of x86 Cores
#14Oh em gee ... what a contentless interview. "We made it wider and deeper". Gosh. Why didn't anyone think about doing that before?
Some examples of very interesting, non-obvious content:
* Even if store ports are kept fixed (2 in his example), adding store address generators (up to 4 in his example) actually improves performance, because it frees up load port dependencies. * Within the same core, they use two different styles of load/address address contention mechanisms which he describes as two tables, one with explicit "allows" and the other one with explicit "denies" -- which of course end up converging (I understand it refers to two different encodings which vary in what is stored). * Between cores, they have completely separate teams which reach different designs for things like this. * It was interesting to me to discover how isolated the different core design teams work (which makes sense) * It was interesting to me to picture the load/store address contention subsystem, which must be quite complex and needs to be really fast.
And I stop listing, re different types of workloads, gaming workloads being similar to DB workloads, and even more similar between them than to SPEC benchmarks and so on.
Just go read the interview if you're interested in CPU design!
[1] mostly automated: at least the dialog name labels seem to be hand-edited, as one of them has a typo
Re: Interviewing Intel's Chief Architect of x86 Cores
#15Oh em gee ... what a contentless interview. "We made it wider and deeper". Gosh. Why didn't anyone think about doing that before?
https://chatgpt.com/share/68ef6cc3-1c48-8013-a545-905af89fbc... I asked chatgpt to give a contentful summary of the interview, it seems to be more or less accurate, albeit surface level. If anyone is interested. It gets the "why" but not the "how". Maybe someone here can prompt it further to speculate on the "how". I don't think I'll be able to verify its output well enough to do that.
Re: Interviewing Intel's Chief Architect of x86 Cores
#16Oh em gee ... what a contentless interview. "We made it wider and deeper". Gosh. Why didn't anyone think about doing that before?
He is no Jim Keller, and the mostly[1] automated transcript makes it read cringe, but it is not at all devoid of content. Some examples of very interesting, non-obvious content: * Even if store ports are kept fixed (2 in his example), adding store address generators (up to 4 in his example) actually improves performance, because it frees up load port dependencies. * Within the same core, they use two different styles…
Re: Interviewing Intel's Chief Architect of x86 Cores
#17Not a lot of novel information either.
Re: Interviewing Intel's Chief Architect of x86 Cores
#18Oh em gee ... what a contentless interview. "We made it wider and deeper". Gosh. Why didn't anyone think about doing that before?
He is no Jim Keller, and the mostly[1] automated transcript makes it read cringe, but it is not at all devoid of content. Some examples of very interesting, non-obvious content: * Even if store ports are kept fixed (2 in his example), adding store address generators (up to 4 in his example) actually improves performance, because it frees up load port dependencies. * Within the same core, they use two different styles…
What made the transcription "cringe"? I'd like to believe it's accurate.
Re: Interviewing Intel's Chief Architect of x86 Cores
#19Earlier quoted context omitted.
https://chatgpt.com/share/68ef6cc3-1c48-8013-a545-905af89fbc... I asked chatgpt to give a contentful summary of the interview, it seems to be more or less accurate, albeit surface level. If anyone is interested. It gets the "why" but not the "how". Maybe someone here can prompt it further to speculate on the "how". I don't think I'll be able to verify its output well enough to do that.
I'm not sure what you expect to get out of this. How do you make a "contentful summary" of a contentless interview? Where do you get the content from?
Re: Interviewing Intel's Chief Architect of x86 Cores
#20Oh em gee ... what a contentless interview. "We made it wider and deeper". Gosh. Why didn't anyone think about doing that before?