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Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

zeroasic.com

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Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#11

Post by adwn »

topspin wrote: post #10
polalavik wrote: post #4

Earlier quoted context omitted.

I know of a few vendor tools whose application size is measured in the multi-hundred of GBs

How does that happen? When I see this, I suspect the vendor is operating under conditions that approach absolute chaos: dumping whatever junk someone imagines might be necessary into the stack with zero resistance, for years on end. Zero effort spent on any factoring that might threaten redundancy.

Xilinx toolchain installations used to include a file which was just the concatenation of the license files of every single open source library they were using somewhere inside any of their own software. Now if you installed two or more components of their toolchain (for example, Vivado, Vitis, and PetaLinux) into the shared installation directory, this same file was installed several times as well. Together, they made up something like 1.5 GiB alone.

I think they've fixed this only a year ago or so.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#12

Post by ithkuil »

adwn wrote: post #11
topspin wrote: post #10

Earlier quoted context omitted.

How does that happen? When I see this, I suspect the vendor is operating under conditions that approach absolute chaos: dumping whatever junk someone imagines might be necessary into the stack with zero resistance, for years on end. Zero effort spent on any factoring that might threaten redundancy.

Xilinx toolchain installations used to include a file which was just the concatenation of the license files of every single open source library they were using somewhere inside any of their own software. Now if you installed two or more components of their toolchain (for example, Vivado, Vitis, and PetaLinux) into the shared installation directory, this same file was installed several times as well. Together, they ma…

Seems a good candidate for a file that can be kept in a compressed form

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#14

Post by adwn »

dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

As much as I wish this would come true, there's little chance for a full, end-to-end open source toolchain for Xilinx or Altera FPGAs that's competitive with the vendor tools. The reason for this is that there's no publicly available documentation of the signal routing configuration or the bitstream format, which are required for the final two steps in the chain. I don't see the two market leaders releasing this information anytime soon, and reverse engineering it from the data files is probably rather difficult.

The synthesis discussed in the linked page is one of the earliest steps, and from the point of view of open source implementations, the simplest one, because all necessary information is freely available.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#15

Post by aappleby »

adwn wrote: post #14
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

As much as I wish this would come true, there's little chance for a full, end-to-end open source toolchain for Xilinx or Altera FPGAs that's competitive with the vendor tools. The reason for this is that there's no publicly available documentation of the signal routing configuration or the bitstream format, which are required for the final two steps in the chain. I don't see the two market leaders releasing this info…

"there's no publicly available documentation of the signal routing configuration or the bitstream format"

Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#16

Post by robinsonb5 »

aappleby wrote: post #15
adwn wrote: post #14

Earlier quoted context omitted.

As much as I wish this would come true, there's little chance for a full, end-to-end open source toolchain for Xilinx or Altera FPGAs that's competitive with the vendor tools. The reason for this is that there's no publicly available documentation of the signal routing configuration or the bitstream format, which are required for the final two steps in the chain. I don't see the two market leaders releasing this info…

"there's no publicly available documentation of the signal routing configuration or the bitstream format" Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

The reverse engineering efforts are impressive (though as I understand it, limited to Xilinx series 7 and Cyclone V) but without robust and reliable timing data to go with the rest of the chip data, they can't give you the same level of confidence that a design will work across a range of a devices and operating conditions.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#17

Post by robinsonb5 »

st_goliath wrote: post #8
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

One thing I will say in favour of the Gowin IDE - it does seem to be much more lightweight than the larger vendors' tools. For smaller designs it will often go from zero to bitstream in less time than Quartus or Vivado would have taken to even start synthesizing.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#18

Post by adwn »

aappleby wrote: post #15
adwn wrote: post #14

Earlier quoted context omitted.

As much as I wish this would come true, there's little chance for a full, end-to-end open source toolchain for Xilinx or Altera FPGAs that's competitive with the vendor tools. The reason for this is that there's no publicly available documentation of the signal routing configuration or the bitstream format, which are required for the final two steps in the chain. I don't see the two market leaders releasing this info…

"there's no publicly available documentation of the signal routing configuration or the bitstream format" Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

> Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

Please provide a source for this claim. Yosys, for example, can't route [1] designs even for Xilinx 7-series devices, and that architecture has been introduced 15 years ago.

[1] Not to be confused with synthesis, mapping, or placing, all of which come earlier in the flow, and for all of which sufficient information is public available.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#19

Post by rowanG077 »

This is not a separate synthesis tool. This is just a yosys plugin and only works for their own FPGAs. Kind of leaves a bad taste in my mount that they choose to advertise this as their own synthesis tool when it isn't. I'm curious why they didn't work together with upstream.

Also looking to their full stack it seem they use VPR/VTR instead of nextpnr for routing. That seems like a backwards choice.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#20

Post by Ygg2 »

st_goliath wrote: post #8
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

> and no, a 50 line comment block with a German transcription of the code below is not documentation

You had it good back then. Now it's a one-line comment in Chinese. Line is 300 characters wide. /Yorkshire men skit.

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