Earlier quoted context omitted.
> and it's also in a class of its own in workloads heavy on AVX-512, though they might be a bit niche. It'll be interesting to see if it remains niche - I do a fair bit of work on graphics rendering (some games, some not) and there's quite a bit in avx512 that interests me - even ignoring the wider register width. A lot of pretty common algorithms we use can be expressed a fair bit easier and simpler using some of th…
> But AMD's implementation doesn't seem to have this problem From an article: > Does Zen5 throttle under AVX512? > Yes it does. Intel couldn't get away from this, and neither can AMD. Laws of physics are the laws of physics. > The difference is how AMD does the throttling ... Further details in the article [1]. Discussed here on HN: [2], [3]. [1] https://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teard... [2] htt…
From the linked numberworld blog:
> Thus on Zen4 and Zen5, there is no drawback to "sprinkling" small amounts of AVX512 into otherwise scalar code. They will not throttle the way that Intel does.
This is exactly the use case I'm talking about - relatively small chunks of avx512-using code spread throughout the codebase. Larger chunks of work tend to be worth passing over to the GPU already.