So, what this project misses, which is quite hard to capture if you think of gates being just on off switches, is the fact that signals are not instantaneous, and everything runs in parallel. As the AND gate 4 gates up the chain switches the NOT gate 4 gates down the chain starts to send different and unstable signals which may or may not be interpreted as a 1 or 0 in the downstream gate. That's the reason computers…
The game Silicon Zeroes ( https://store.steampowered.com/app/684270/Silicon_Zeroes/ ) teaches this. It starts out with components computing their outputs instantaneously, but then introduces the concept of microticks such that the output of a component is unstable until its inputs are stable enough for some time, so the clock speed must be adjusted according to the largest delay in all circuit paths. The game starts…
I don't know how CPUs work so I simulated one in code (2019)
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Re: I don't know how CPUs work so I simulated one in code (2019)
#12I was once shown a dos-based CPU simulator back in the mid/late 90s. From memory it showed instruction decode, execution, cache and memory. Unfortunately I've never been able to find it, because all the google results are about running DOS games and/or DOSBox.
A search engine won't help you, but a local llm might.
Re: I don't know how CPUs work so I simulated one in code (2019)
#13What I learned from Ben Eater is that a non-cheaty solution would have been to write a simple UART serial "device" and then interacted with the CPU via serial communication with a terminal.
Re: I don't know how CPUs work so I simulated one in code (2019)
#14So, what this project misses, which is quite hard to capture if you think of gates being just on off switches, is the fact that signals are not instantaneous, and everything runs in parallel. As the AND gate 4 gates up the chain switches the NOT gate 4 gates down the chain starts to send different and unstable signals which may or may not be interpreted as a 1 or 0 in the downstream gate. That's the reason computers…
You only got (back in my day) NOT (the torch) and OR gates (wiring next to each other), and everything was built out of them. Signal repeaters had delay, the gates had delay, so you naturally had to build a clock to synchronise it all.
The main benefit that I enjoyed was that you could see the signals physically propagating from one end of your cpu to the other in real time (clock cycles were in the range of 1-4 seconds), flowing from the instructing fetching, decoding, dispatch, logic, writing to back memory, etc. Seeing signals slowly crawl from one end to the other naturally introduced you to pipelining (it even happens naturally if you increase the clock without thinking about what will actually happen: the next instruction starts decoding before the previous one is done, more parts of your cpu start lighting up at once, and oops now you have a pipelined cpu).
Even the scales match; many learners are surprised that the actual ALU is the tiny thing in the corner that you can barely see, and all the giant stacks of rows you actually saw is memory and cache. Even in minecraft, most of your CPU is not logic :)
Also really taught me how asics are much faster: you could build a tiny compact multiplier that multiplied hundreds of times faster than your giant cpu running a multiplication algorithm.
Looks like they community I learnt from is still around actually https://openredstone.org/, even if all the old forum posts seems to be gone now. There were some geniuses on that place building computers with multi-tier caches, full pipelining, out-of-order (albeit primitive) execution, SIMD-capable CPUs, all in redstone.
Re: I don't know how CPUs work so I simulated one in code (2019)
#15If, for fun, I wanted to train an ML model on a ton of CPU instructions (which each predicted state/label being the state of the registers), does anyone have any clue how to gather that kind of data?
If you need real instructions (without an emulator like qemu doing its own translation and messing up timing), you could use a simulator like Gem5. That’s a bit more work and a lot more compute per simulated instruction.
Re: I don't know how CPUs work so I simulated one in code (2019)
#16Re: I don't know how CPUs work so I simulated one in code (2019)
#17Re: I don't know how CPUs work so I simulated one in code (2019)
#18So, what this project misses, which is quite hard to capture if you think of gates being just on off switches, is the fact that signals are not instantaneous, and everything runs in parallel. As the AND gate 4 gates up the chain switches the NOT gate 4 gates down the chain starts to send different and unstable signals which may or may not be interpreted as a 1 or 0 in the downstream gate. That's the reason computers…
Here I was thinking[1][2] the reason computers had clocks was merely a consequence of the synchronous architectures that characterize them.
[1] https://en.wikipedia.org/wiki/Metastability_(electronics)
[2] https://en.wikipedia.org/wiki/Quasi-delay-insensitive_circui...
Re: I don't know how CPUs work so I simulated one in code (2019)
#19Re: I don't know how CPUs work so I simulated one in code (2019)
#20His channel has a lot of other really great stuff on general electronics as well.