We all knew this was coming, but my question is what's the topology? The same as the regular Pi5, with the RP1 southbridge built-in and only one PCIe lane exposed for the user, or does the CM5 leave off the RP1 and break out all five PCIe lanes for user shenanigans? They have a bare chip supply chain set up from the RP2040, so they could sell the RP1 separately for those who want to integrate it onto their carrier bo…
It looks like the CM5 still has one PCIe lane. https://pip.raspberrypi.com/categories/945-forward-guidance
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