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What’s the Smallest Variety of CHERI? (2022)

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Re: What’s the Smallest Variety of CHERI? (2022)

#11
post #2

Read also the follow-up post, "First steps in CHERIoT Security Research" https://msrc.microsoft.com/blog/2023/02/first-steps-in-cheri... Ironically, the future of secure computing is bringing back memory tagging.

> Ironically, the future of secure computing is bringing back memory tagging I find it's often the case exciting new tech turns out to have its fundamental principles described in a paper from the 60s or 70s ;)

This seems par for the course in computer architecture, and probably computer systems in general.

Part of it seems to be that technological improvements (such as better silicon and faster compute/storage/communication as well as more input data) can enable formerly impractical ideas to scale up/out and become useful.

Another part is that the performance and power wall has forced CPU designers to think about other ways to improve CPUs, such as improving security and reliability. Maybe the market will finally be willing to trade off some cost and speed for better security and reliability.

Lastly, software which used to be impractical or overly expensive because of resource usage can often run easily on modern hardware.

Re: What’s the Smallest Variety of CHERI? (2022)

#12

Since this was published MS have published the RTL of their CHERIoT Ibex variant: https://github.com/microsoft/cheriot-ibex . There's also the full technical report and software stack including RTOS available: https://www.microsoft.com/en-us/research/publication/cheriot... I always thought it made more sense to try introducing capabilities on higher-performance applications (all the stuff you might use an arm A-class…

I'd say another factor is that microcontrollers are less equipped to run memory checking tools like Valgrind or ASAN than desktops, and lack separate address spaces between processes, increasing the "blast radius" of memory errors.
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