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Are these programmable by the end-user? The "software programmability" section describes "Vitis AI" frameworks supported. But can we write our own software on these?
Is this card FPGA-based?
EDIT: [1] more info on the AI-engine tiles: scalar cores + "adaptable hardware (FPGA?)" + {AI+DSP}.
[1] https://www.xilinx.com/products/technology/ai-engine.html
AMD XDNA – Versal AI Core / 2nd-gen AIE-ML tiles Are these programmable by the end-user? The "software programmability" section describes "Vitis AI" frameworks supported. But can we write our own software on these? Is this card FPGA-based? EDIT: [1] more info on the AI-engine tiles: scalar cores + "adaptable hardware (FPGA?)" + {AI+DSP}. [1] https://www.xilinx.com/products/technology/ai-engine.html
> [...]
> **: @10 fps, H.264/H.265
Is 10 fps a standard measure for this kind of thing?
16gb RAM / 96 video channels ... I haven't done any of that work but it feels like they expect that "96" not to be fully used in practice.
What TOPS means exactly in "... TOPS*|(INT8) 404 ..." ?
TOPS - Trillions of Operations Per Second, used as a benchmark to figure out the performance of the accelerator. In my experience, mostly a marketing number, higher TOPS doesn't actually mean it'll be faster than something with a lower TOPS. As always, you need to do your own benchmarks with your use case in mind.
AMD XDNA – Versal AI Core / 2nd-gen AIE-ML tiles Are these programmable by the end-user? The "software programmability" section describes "Vitis AI" frameworks supported. But can we write our own software on these? Is this card FPGA-based? EDIT: [1] more info on the AI-engine tiles: scalar cores + "adaptable hardware (FPGA?)" + {AI+DSP}. [1] https://www.xilinx.com/products/technology/ai-engine.html
It's possible that AMD could have reworked an existing Xilinx design to incorporate RDNA chiplets in place of some of the FPGA-gate-grid chiplets, creating a heterogeneous mesh; but I find it just as likely that AMD just took their VLSI for an RDNA core and loaded it onto the existing FPGA.
AMD XDNA – Versal AI Core / 2nd-gen AIE-ML tiles Are these programmable by the end-user? The "software programmability" section describes "Vitis AI" frameworks supported. But can we write our own software on these? Is this card FPGA-based? EDIT: [1] more info on the AI-engine tiles: scalar cores + "adaptable hardware (FPGA?)" + {AI+DSP}. [1] https://www.xilinx.com/products/technology/ai-engine.html
Says RDNA based which is AMD's GPU tech.
> High-Density Video Decoder**: 96 channels of 1920x1080p > [...] > **: @10 fps, H.264/H.265 Is 10 fps a standard measure for this kind of thing?
Douglas Adams said we'd have robots to watch TV for us. That seems to be the designed use case for this. 16gb RAM / 96 video channels ... I haven't done any of that work but it feels like they expect that "96" not to be fully used in practice.
AMD XDNA – Versal AI Core / 2nd-gen AIE-ML tiles Are these programmable by the end-user? The "software programmability" section describes "Vitis AI" frameworks supported. But can we write our own software on these? Is this card FPGA-based? EDIT: [1] more info on the AI-engine tiles: scalar cores + "adaptable hardware (FPGA?)" + {AI+DSP}. [1] https://www.xilinx.com/products/technology/ai-engine.html