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Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

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Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#11

Post by readonlybarbie »

habitue wrote: post #10
readonlybarbie wrote: post #8

Earlier quoted context omitted.

Noob question- must one write avx512 assembly directly by hand, or is this something a c compiler would do for you?

Potentially both. Most compilers have vectorization optimizations if you compile for an architecture that supports it. However, a lot of software is compiled on one machine to be run on potentially many possible architectures, so they target a very lowest common denominator arch like x86-64. This will have some SIMD instructions but (I don't think) AVX-512. So if a developer wants to ensure those instructions are use…

thanks for that! so it sounds like, if i purchase a chip that supports avx512, and run an operating system and compiler that supports avx512, i can write "plain old c code" with a minimal amount of compiler arguments and compile that code on my machine (aka not just running someone else's binary). and then the full power of avx512 is right there waiting for me? :)

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#12

Post by celrod »

stabbles wrote: post #9
moonchild wrote: post #6

Earlier quoted context omitted.

Most of what's interesting about avx512 is the new instructions; the wider vectors are just icing on the cake. You would need to rewrite your code regardless.

I wonder to what extent compilers even emit avx512 instructions apart from the common ones (load, store, shuffle, arithmetic) in case you don’t want to manually optimize for sse / avx / avx2 / avx512.

How much code is compiled with `-march=native` or function multiversioning? I would guess the percentage is relatively small, at least when it comes to distributed binaries.

Compiler autovectorizers also aren't very good at producing fast AVX512 code, so most of the benefit would probably come from using optimized libraries like Intel's MKL or simdjson.

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#13

Post by chris6f »

snvzz wrote: post #5

AVX-512 is wider, but also needs special instructions to leverage the hardware. This is unlike RISC-V V extension, where the same code will run and utilize the hardware, regardless of vector unit width.

Vector length agnostic programming has its own share of problems. I'm not familiar with the RISC-V V extension, but I assume it's similar to ARM's SVE. There's a good critical look at SVE and VLA here: https://gist.github.com/zingaburga/805669eb891c820bd220418ee...

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#14

Post by ryao »

moonchild wrote: post #6
snvzz wrote: post #5

AVX-512 is wider, but also needs special instructions to leverage the hardware. This is unlike RISC-V V extension, where the same code will run and utilize the hardware, regardless of vector unit width.

Most of what's interesting about avx512 is the new instructions; the wider vectors are just icing on the cake. You would need to rewrite your code regardless.

Using the RISC-V V vector instructions means that the underlying hardware vector width can change and the code will automatically take advantage of the larger width.

That said, many of the avx512 instructions are simply extended width AVX2/avx2 instructions. The interesting things about it are really the increased width and the additional registers. Not many of the new instructions that are not bitwidtg extended versions of the old ones are particularly interesting since Intel had already implemented most of the interesting things for smaller vector widths.

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#15

Post by sakras »

ajross wrote: post #3

> These results suggest that AMD Zen 4 is matching Intel Ice Lake in AVX-512 performance. Given that the Zen 4 microarchitecture is the first AMD attempt at supporting AVX-512 commercially, it is a remarkable feat. Um... Ice Lake shipped over three years ago. I mean, there's a real question as to whether or not "senselessly wide SIMD" is a good or bad feature in a datacenter part, and how or whether AMD should attemp…

The Ice Lake chips being benchmarked against are server chips, while the 7950X Zen 4 chip used is a consumer chip. So while Ice Lake has been out for a while, it’s also several times more expensive. It’s also worth noting that it took Intel several generations of trying AVX512 to get it working well, so AMD doing it first try really is impressive (even if they did cheat by just having AVX512 be double pumped AVX2).

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#16

Post by ryao »

stabbles wrote: post #9
moonchild wrote: post #6

Earlier quoted context omitted.

Most of what's interesting about avx512 is the new instructions; the wider vectors are just icing on the cake. You would need to rewrite your code regardless.

I wonder to what extent compilers even emit avx512 instructions apart from the common ones (load, store, shuffle, arithmetic) in case you don’t want to manually optimize for sse / avx / avx2 / avx512.

Even if you use the GNU C vector extension to explicitly give the compiler ways of optimizing C, it is not very good at generating good vector code:

https://github.com/openzfs/zfs/pull/14234#issuecomment-13345...

A bug report has been filed with GCC for one of the issues. LLVM is much better here, but not perfect, or at least that has been my experience when trying to have the compiler generate assembly for an explicitly vectorized fletcher4 implementation.

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#17

Post by brrrrrm »

readonlybarbie wrote: post #8
moonchild wrote: post #6

Earlier quoted context omitted.

Most of what's interesting about avx512 is the new instructions; the wider vectors are just icing on the cake. You would need to rewrite your code regardless.

Noob question- must one write avx512 assembly directly by hand, or is this something a c compiler would do for you?

typically if it's available, compilers will use the avx512 register file. This means you'll see things like xmm25 and ymm25 (128 and 256 bit registers) and those are avx512 only. However, compilers using 512-wide instructions is kinda rare from what I've seen

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#18

Post by moloch-hai »

readonlybarbie wrote: post #8
moonchild wrote: post #6

Earlier quoted context omitted.

Most of what's interesting about avx512 is the new instructions; the wider vectors are just icing on the cake. You would need to rewrite your code regardless.

Noob question- must one write avx512 assembly directly by hand, or is this something a c compiler would do for you?

Generally you are better off coding with "intrinsics", compiler extensions that represent the instructions more symbolically, if in fact the compiler offers what you need.

I am not sure the really interesting AVX-512 instructions have intrinsics yet. For those it's asm or nothing.

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#19

Post by moloch-hai »

sakras wrote: post #15
ajross wrote: post #3

> These results suggest that AMD Zen 4 is matching Intel Ice Lake in AVX-512 performance. Given that the Zen 4 microarchitecture is the first AMD attempt at supporting AVX-512 commercially, it is a remarkable feat. Um... Ice Lake shipped over three years ago. I mean, there's a real question as to whether or not "senselessly wide SIMD" is a good or bad feature in a datacenter part, and how or whether AMD should attemp…

The Ice Lake chips being benchmarked against are server chips, while the 7950X Zen 4 chip used is a consumer chip. So while Ice Lake has been out for a while, it’s also several times more expensive. It’s also worth noting that it took Intel several generations of trying AVX512 to get it working well, so AMD doing it first try really is impressive (even if they did cheat by just having AVX512 be double pumped AVX2).

Double-pumped is fine: what matters is the new semantics implemented that cannot be expressed efficiently in previous ISAs.

Re: Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

#20

Post by tedunangst »

wtallis wrote: post #4
svnpenn wrote: post #2

I saw this once before, and both times, it's pretty shocking. Is this really something that needs to be inside the CPU itself? I don't want my CPU doing this. I would rather just take the performance hit and keep the CPU "dumb".

Are you saying you don't want your CPU to have SIMD/vector capabilities, or you want it to have a limited SIMD instruction set without the extra flexibility that AVX-512 brings, or have you wildly misinterpreted the headline (twice?) to assume that AVX-512 adds special-purpose instructions for Unicode conversions?

Any instructions beyond NAND are clearly bloat.
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