Earlier quoted context omitted.
“20xx - Year of the Linux desktop”
2xxx
Moore’s Law is dead – Long live the chiplet
11–20 of 123 posts
Re: Moore’s Law is dead – Long live the chiplet
#12Re: Moore’s Law is dead – Long live the chiplet
#13Shocking
Re: Moore’s Law is dead – Long live the chiplet
#14> With $100 million in funding, the IDEAS and POSH programs ... aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards. If successful, the programs “will change the economics of the industry,” enabling companies to design in relatively low-volume chips that would be prohibitive today.
2017 vision, slide #22, https://www.darpa.mil/attachments/eri_design_proposers_day.p...
My DARPA dream
$ git clone https://github.com/darpa/idea
$ git clone https://github.com/darpa/posh
$ cd posh
$ make soc42
ERI Summit 2019, Intelligent Design of Electronic Assets (IDEA) & Posh Open Source Hardware (POSH), https://youtube.com/watch?v=pJubnAN3VKwUCSD OpenRoad, https://theopenroadproject.org/ & https://vlsicad.ucsd.edu/Publications/Conferences/378/c378.p...
> OpenROAD is a front-runner in open-source semiconductor design automation tools and know-how. Our project reduces barriers of access and tool costs to democratize system and product innovation in silicon. The OpenROAD tool and flow provide autonomous, no-human-in-the-loop, 24-hour RTL-GDSII capability to support low-overhead design exploration and implementation through tapeout. We welcome a diverse community of designers, researchers, enthusiasts and entrepreneurs who use and contribute to OpenROAD to make a far-reaching impact.
https://semiengineering.com/will-open-source-eda-work/
> All the big EDA providers, as well as leading chip companies, are active contributors to ERI projects. In fact, Cadence, Synopsys, Mentor, NXP, Intel, IBM, Intel, Qualcomm, Arm, Nvidia, Analog Photonics, SRI International and Applied Materials all have contributed speakers and engineers or materials to ERI effort ... the key to getting industry players to accept open-source EDA is whether it makes the design process more efficient without breaking anything—and whether it is possible to extract decades worth of design experience from libraries of millions of existing designs and use that to spot errors in real time in existing designs.
Re: Moore’s Law is dead – Long live the chiplet
#15Re: Moore’s Law is dead – Long live the chiplet
#16Moore’s law was a marketing road map for intel. It was basically a monopolistic warning from one of the founders not to release new products too fast so the company wouldn’t burn out. It worked. But it’s not some scientific or physical law and I hate when people refer to it as such.
According to the article, Moore's Law predates the founding of Intel by several years.
Re: Moore’s Law is dead – Long live the chiplet
#17> However, as it has in the past, the semiconductor ecosystem is adapting and as Chiplet technology builds traction, we will very likely see a period of accelerating innovation and new market opportunities opening as we move forward.
The whole premise is that chip innovation (and overall computing power) is continuing to accelerate, even though "Moore's Law as we've known it" has ended
Re: Moore’s Law is dead – Long live the chiplet
#18Moore’s law was a marketing road map for intel. It was basically a monopolistic warning from one of the founders not to release new products too fast so the company wouldn’t burn out. It worked. But it’s not some scientific or physical law and I hate when people refer to it as such.
Intel can't dictate the technology advances of other competitors
Re: Moore’s Law is dead – Long live the chiplet
#19https://en.wikipedia.org/wiki/Chiplet
This seems to be about the third reason listed:
> Known good die (KGD): chiplets can be tested before assembly, improving the yield of the final device
Problem:
> In general, a killer defect is defined as a defect that is 20% the size of the fabrication node. For
> example, a defect that is less than 9nm may be acceptable for the 45nm fabrication node, but a defect
> larger than 2.8nm would be defined as a “killer” defect for the 14nm fabrication node. For the 5nm
> fabrication node, a defect measuring only 1nm could be a killer.
>
> This is one of the primary reasons that it has become increasingly difficult to yield large monolithic
> ICs (as measured in die area) when using leading edge fabrication process technology
Solution: I understood it from the visual explanation in the first chip image (AMDArt2 png) and its description in this article:https://www.nextplatform.com/2021/06/09/amd-on-why-chiplets-...