Intel announces new FPGA families

I don't think STM32 MCUs are that special, not are they related to Intel FPGAs. There are plenty of STM32 clones out there and manufacturers have moved on.

Yes, but that's not the problem. The problem is these Agilex devices are insane overkill for that task, and you likely won't be able to buy the SKUs in a reasonable form factor or price for that use case. The Mister worked so well because the actual design of the device has the right blend of peripherals/compute and Intel/terASIC ate the NRE to design and manufacture it, and that's because they intended it use it to teach and educate people and needed a lot of volume for that. Agilex isn't a teaching part. It's their most advanced top-of-the-line part with its own logic design requirements that differentiate it from earlier lines (Arria 10 and prior.)

You likely aren't going to see "consumer-oriented" Agilex-powered devices in similar form factors anytime soon; most of the compute power of the fabric would be completely wasted without fast peripherals/storage anyway (the fabric can be clocked very high if you pipeline enough) and the shipping volume to make the boards attractive/low-price enough would need to be pretty decent. This means the board would actually end up expensive; why pay so much for the FPGA if all the I/O sucks? But good I/O is expensive. The Agilex parts are some of Intel's most complex devices on their latest "Intel 7" process too, it's not cheap.

I guess it's maybe something that would be possible to crowdfund in low volumes, but it's a truly huge amount of work even before you get to price. Designing the board, getting the software and tools working, documentation, that's before you even manufacture. And realistically there are probably other FPGA options that would be cheaper and more readily available. Something like a Kintex-7, or Arria 10 part would probably do just as well for significantly cheaper, I'd think, but it's hard to guess unless you have more concrete requirements in terms of LEs/memory/clock speeds.

Maybe if you pray they will make an Agilex-D PCIe developer kit that "only" costs $2k USD, requires tiny fans that sound like jet engines, and has 1 HDMI out.

You can in theory clock the Agilex/S10 parts up-to 1GHz, but something like 600-700MHz sounds more realistic, yes. (Note that this is in the same ballpark as what Virtex UltraScale+ can do too.)

Also, regarding point 1 -- and I'm sure you know this already, but this is for everyone else -- you have to be careful when talking about "Logic Elements" with most of the industry because, even when describing 6-LUT parts, Intel/Xilinx often list "Logic Element Count" to mean "Number of logic elements when considered on a normalized 4-LUT basis." Both Intel and Xilinx do this and I guess it kind of makes sense; only their highest end parts are non-4LUTs so they're the odd ones out when compared to everything else in the industry. So when you read "Number of LEs", they normalize it to 4-LUTs since that's what your competitors (or older parts) would use, when accounting for density.

For example I have a Stratix 10 card in my server that has "Millions of logic elements" when you look at the product tables, but that is taken on a normalized 4-LUT basis. There are actually "only" about 900,000 ALMs on the device, with each ALM being 8-input and fracturable. So TL;DR the numbers between the low-end Agilex-D part and the Cyclone part is maybe not that far off.

I did mean 25% faster, though it was a guesstimate. That was comparing Agilex to Agilex D, not Cyclone V to Agilex D.

FPGA logic in simple terms consists of LUTs (look up tables, used to implement gates) and registers. The LUTs can be chained several times until they connect to a register. Registers are clocked at a frequency.

Now the max frequency is calculated using the maximum time from a register output, through a bunch of LUTs to reach another register. So it depends how long the chain is.

Its more complex than that in reality since there is also the time for the clock to propagate and to route the signals around. Fortunately the software takes care of that.

I don't really know how maximum frequency is specified in the specs, but I guess it'd be something like an ideal register->single LUT->register without much routing.

This is the official statement of the Raspberry Pi Foundation on this topic:

> https://www.raspberrypi.com/news/production-and-supply-chain...

Excerpt:

"As we’ve said before, the current situation is as much a demand shock as a supply shock: demand for Raspberry Pi products increased sharply from the start of 2021 onwards, and supply constraints have prevented us from flexing up to meet this demand, with the result that we now have significant order backlogs for almost all products. In turn, our many resellers have their own backlogs, which they fulfil when they receive stock from us.

These backlogs absorb Raspberry Pi units as fast as (or faster than!) we can produce them, with the result that little of our production volume ends up being immediately available on reseller websites. Where units do appear, bots often attempt to scalp stock which is then resold at higher prices elsewhere."

Different perspectives are given in the answer https://raspberrypi.stackexchange.com/questions/139020/why-i...

In particular, the following alternative explanations are discussed (which don't exclude each other):

- industrial customers are given priority

- there are currently deep changes in the Raspberry Pi Foundation happening