Some of these are standard, a few are genuinely clever, but many are bad designs and I'd never let someone tape them out in production.
2. Connecting the body terminal to something other than the highest voltage is dangerous and we rarely do it except in switches and diff pairs. We'd never do something like this. You can't even connect the nmos body to the gate unless you're using "deep" nwells which is an expensive process step that most people seem to avoid these days
3. I hate it when foundries do this in their standard cell libraries. Its an extremely weak pulldown and I've seen problems in production caused by using this structure. You can make a much better structure with a third transistor and positive feedback where devices still aren't connected to the supplies, but you get a stronger pull.
4-6. These are current-mode logic, but you never see them made this way because they're slow and high power. Instead they're usually made with a tail current source on the "bottom" and resistors on top, which keeps all transistors in a faster operating region. They get used often in RF clock dividers.
16. Again, connecting the body is dangerous, especially when the potential is somewhat unknown, but this does get used in extremely low power/low voltage applications.
I didn't get through all of them, but it made me wonder - with two 4-terminal devices, how many possible configurations can you actually make?