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“Risc V greatly underperforms”

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Re: “Risc V greatly underperforms”

#11
So a few decades ago.. I knew a guy who was one of the chief designers of RISC procs at MIPs

Yeah - he was addicted to prostitutes...

This guy was doing amazing engineering work and we talked at length about designing a system for basically what became rack-mount trays

But he was so distracted by his addiction to prostitutes...

Re: “Risc V greatly underperforms”

#13
I think talking about ISAs as better or worse than one another is often a bad idea for the same reason that arguing about whether C or Python is better is a bad idea. Different ISAs are used for different purposes. We can point to some specific things as almost always being bad in the modern world like branch delay slots or the way the C preprocessor works but even then for widely employed languages or ISAs there was a point to it when it was created.

RISC-V has a number of places it's employed where it makes an excellent fit. First of all academia. For an undergrad making building the netlist for their first processor or a grad student doing their first out of order processor RISC-V's simplicity is great for the pedagogical purpose. For a researcher trying to experiment with better branch prediction techniques having a standard high-ish performance open source design they can take and modify with their ideas is immensely helpful. And for many companies in the real world with their eyes on the bottom line like having an ISA where you can add instructions that happen to accelerate your own particular workload, where you can use a standard compiler framework outside your special assembly inner loops, and where you don't have to spend transistors on features you don't need.

I'm not optimistic about RISC-V's widescale adoption as an application processor. If I were going to start designing an open source processor in that space I'd probably start with IBM's now open Power ISA. But there are so many more niches in the world than just that and RISC-V is already a success in some of them.

Re: “Risc V greatly underperforms”

#14
Few years ago, I designed my own ISA. In that time I investigated design decisions in lots of ISAs and compared them. There was nothing in the RISC-V instruction set that stood out to me, like for example, the SuperH instruction set, which is remarkably well designed.

Edit: Don't get me wrong, I don't think RISC-V is "garbage" or anything like that. I just think it could have been better. But of course, most of an architecture's value comes from its ecosystem and the time spent optimizing and tailoring everything...

Re: “Risc V greatly underperforms”

#15
post #12

Why do these half baked slam pieces always make it to the top of HN?

Many people upvote things not necessarily because they agree with them, but rather to bump it in hopes that someone with good insights will chime in in the comments section.

This especially applies to potentially controversial things.

Re: “Risc V greatly underperforms”

#16
post #2

The idea is to use the compressed instruction extension. Then two adjacent instructions can be handled like a single “fat” instruction with a special case implementation. That allows more flexibility for CPU designs to optimize transistor count vs speed vs energy consumption. This guy clearly did not look at the stated rationale for the design decisions of RISC-V.

Compressed instructions and macro-fusion aren't magical solutions. It's not always possible to convince the compiler to generate the magical sequence required, and it actually makes high-performance implementations (wide superscalar) more difficult thanks to the variable width decoding. Beyond that, compressed instructions are not a 1:1 substitute for more complex instructions, because a pair of compressed instructio…

In the context of gmp, people write architecture-specific assembly for the inner loop anyway.

Besides that, you raise good points on sources of complexity. I’m waiting for the benchmarks once such developments have been incorporated. Everything else is guesswork.

Re: “Risc V greatly underperforms”

#17
A bit of a computer history question: I have never looked at the ISA of the Alpha (referenced in post), but RISC V has always struck me as being nearly identical to (early) MIPS, just without the HI and LO registers for multiply results and the addition of variable length instruction support, even if the core ISA doesn't use them.

MIPS didn't have a flag register either and depended on a dedicated zero register and slt instructions (set if less than)

Re: “Risc V greatly underperforms”

#19
post #12

Why do these half baked slam pieces always make it to the top of HN?

I think the reason is that it ultimately encourages deep and thoughtful conversation. If nothing controversial was ever proposed, the motivation for participating and "proving others wrong" is lessened. It might not be the healthiest way, but I certainly find myself putting a lot more thought into my comments if its a contrary point or in some broader controversial context.

Overall, I feel HN is most fun when a lot of people are in disagreement but also operating in good faith.

Re: “Risc V greatly underperforms”

#20
post #12

Why do these half baked slam pieces always make it to the top of HN?

if for no other reason than to quickly formulate counterarguments. Next time at some meeting or other get together, if someone pipes up with an anti-RISC comment, most people won't be able to quickly refute it. But having had this discussion here, we're inocculated and able to respond with intelligence and experience.
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