At what point does quantum tunnelling become a problem?
It's always been a problem to some degree. Keep in mind that 3nm is a misnomer and has no real physical meaning behind it.
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Samsung Foundry Forum announcements
11–20 of 132 posts
Re: Samsung Foundry Forum announcements
#12At what point does quantum tunnelling become a problem?
First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particula…
The theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm.
You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.
Re: Samsung Foundry Forum announcements
#13I can never remember what xnm means as it varies between companies. In this case, Samsung's 3nm = Intel's 7nm I am still waiting for a standard based on transistor density numbers!
Intel actually renamed their nodes in like with Samsung and TSMC, so Intel 7 (used to called 10nm) is roughly comparable to TSMCs 7nm and Samsungs 8nm
Re: Samsung Foundry Forum announcements
#14There are a few comments saying that 3nm is a marketing term and that the transistors are actually larger - how is this allowed? Isn't it misleading and deceptive?
There’s not really a standard, some feature is probably 3nm, which feature chosen has varied over time and between companies.
Re: Samsung Foundry Forum announcements
#15There are a few comments saying that 3nm is a marketing term and that the transistors are actually larger - how is this allowed? Isn't it misleading and deceptive?
Actually it is all about marketing now, the customers though to whom they market are MNCs with immense cash piles to splurge on microchips. Nobody else can.
See — you rarely ever see so much marketing money spent on an industrial service, and like here seeing Hollywood level gfx on an obscure industry event keynote would've been more laughable than noteworthy 10 years ago.
Without these cash piles, there is no way to finance new fabs, and SEL is fighting for its survival here. Once you are out of the race in semi industry, you can never catch up.
Re: Samsung Foundry Forum announcements
#16Earlier quoted context omitted.
First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particula…
The theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm. You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.
Can't they use a smaller wavelength source? Nothing special about 13nm afaik
Re: Samsung Foundry Forum announcements
#17Earlier quoted context omitted.
The theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm. You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.
Can't they use a smaller wavelength source? Nothing special about 13nm afaik
13nm * 2 is 26nm.
Using a smaller wavelength is kind of useless for the optical lithography, as below this photons will make too many secondary electrons which will reduce the effective resolution. This is the reason X-ray lithography went nowhere.
This is why the ultimate limit of 157nm lithography was also not so far away from EUV. Also somewhere in between 25nm-30nm
This is also why some people suggest resurrecting 157nm — getting nearly same half pitch without maintenance, and expensive tooling of EUV.
Re: Samsung Foundry Forum announcements
#18I can never remember what xnm means as it varies between companies. In this case, Samsung's 3nm = Intel's 7nm I am still waiting for a standard based on transistor density numbers!
It doesn’t relate to any measurement of feature size. It’s just a frustratingly meaningless marketing term.
Re: Samsung Foundry Forum announcements
#19Earlier quoted context omitted.
The theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm. You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.
Can't they use a smaller wavelength source? Nothing special about 13nm afaik
The design of EUV lasers is already completely absurd. It's an awesome piece of engineering, but it's no easier to push the laser wavelength downwards than anything else.
Re: Samsung Foundry Forum announcements
#20Samsung has a dishonorable marketing department. 3nm is not actually 3nm. I'm fed up... OLED is superior so they had to take the path of calling theirs QLED which is actually just an LCD screen with phosphors on top of a blue backlight (and it's nothing new).