Unfortunately, going one layer down, most ASIC tooling is extremely opaque about what it does, and it's hard to share chip designs that are open at all levels (you may have open-source verilog, but the GDSII might have to be closed-source due to vendor NDAs). I suspect that if you have problems with FPGA tooling, you will also have problems with ASIC tooling.
However, the cost of an ASIC on an older node (~65-130 nm) is a lot lower than you think. There are (bad) free design tools and even older nodes may have open PDKs from foundries (the old scalable CMOS processes).
I have been considering starting up a company to build hardware root-of-trust chips along the lines of Titan/Cerberus,but I don't know if there's enough of a customer base out there to make it a reality.