11–20 of 52 posts
this is super awesome! did you build the raytracing stuff from the ground up?
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The screen is connected to the FPGA over VGA. The output resolution is 1024x768 @ 60Hz, but the 3D portion of the screen is rendered at 256x128 @ 30Hz. The design consists of a custom 16-bit CPU (running at 32.6Mhz) and a custom raytracing "GPU" that can handle up to 4 rays in parallel. Input happens via a N64 controller! Those are actually fairly easy to work with at a low level. The code is not public, though I'm c…
Pretty impressive; definitely interested in hearing more. Did you use your Wyre [1] language to develop it? I saw the examples on Github, and seems pretty interesting. Its cuts quite a bit of the verbosity of Verilog. I'll give it a try. [1] https://github.com/nickmqb/wyre
this is super awesome! did you build the raytracing stuff from the ground up?
Thanks! That's correct, I built the ray tracing "GPU" from scratch. It's highly optimized because it needs to trace 256 * 128 * 30 = 0.98 million rays per second on very under powered hardware. It's specifically tailored to fast traversal of voxel grids. There's too many details to go into here, but as I wrote in another comment, I'm considering writing a few blog posts to explain how everything works in more detail!
If you do, I'd love to read them.
How is the rendering performance with large worlds?
The FPGA that I'm using for this (the Lattice iCE40 UP5K) is really limited when it comes to RAM, which is the main constraint when it comes to world size. As per the title, there's only 143kb, which is insanely low for doing any kind of 3D stuff :). 48kb is used by the frame buffer, 19kb for textures, which leaves 76kb. 48kb of that is used for the map, which currently limits it to 32x32x32 blocks. However, I do hav…
Are there any FPGAs out there with an order of magnitude more memory you have considered?
Did you consider porting it to mister?
I just looked up the MiSTer board [1]. They are using a DE10-Nano FPGA [2], which is a lot more powerful than the iCE40 UP5K [3] that I'm using (for comparison, the DE10-Nano has 110,000 lookup elements, whereas the iCE40 UP5K just has 5,280, so ~20x difference!). So porting should be pretty easy. It also opens up opportunities to increase the resolution, frame rate and render distance.
[1] https://github.com/MiSTer-devel/Main_MiSTer/wiki [2] https://www.digikey.com/en/product-highlight/t/terasic-tech/... [3] https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40Ult...
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The FPGA that I'm using for this (the Lattice iCE40 UP5K) is really limited when it comes to RAM, which is the main constraint when it comes to world size. As per the title, there's only 143kb, which is insanely low for doing any kind of 3D stuff :). 48kb is used by the frame buffer, 19kb for textures, which leaves 76kb. 48kb of that is used for the map, which currently limits it to 32x32x32 blocks. However, I do hav…
Thanks for the reply incredible work! Are there any FPGAs out there with an order of magnitude more memory you have considered?
While it would have been easier to use a larger/faster FPGA, part of the fun of such a low level project is to work within harsh constraints and see what can be done regardless :).
If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface: https://github.com/efabless/caravel/blob/master/verilog/rtl/...
The openlane tool converts your verilog all the way down to final ASIC design...
You'd need to license everything Apache 2.0 though. And it would have to be done soon, the deadline is Nov 30th.
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Pretty impressive; definitely interested in hearing more. Did you use your Wyre [1] language to develop it? I saw the examples on Github, and seems pretty interesting. Its cuts quite a bit of the verbosity of Verilog. I'll give it a try. [1] https://github.com/nickmqb/wyre
Yes, I'm using Wyre for this. Feedback is always welcome, so once you've had a chance to try it, don't hesitate to let me know what you think!