This will be interesting once it is finished.
As it is now, it is just a skeleton, and thus not worth the light of day.
Writing a RISC-V Emulator from Scratch
11–16 of 16 posts
Re: Writing a RISC-V Emulator from Scratch
#12Thanks for your interest! I'm an author of this book. This book is very beginning as you mentioned and I'm still working on it.
I already succeeded to run xv6 in my RISC-V emulator and wrote a blog post "Made a RISC-V Emulator Running Xv6": https://d0iasm.github.io/blog/risc-v/2020/04/03/xv6-on-my-ri...
I have 2 different RISC-V emulators and its goals are different:
rvemu (https://github.com/d0iasm/rvemu): Can run xv6. It's trying to support Linux and make it faster in the future.
rvemu-for-book (https://github.com/d0iasm/rvemu-for-book): Reference implementation for the book. Simpler than original one.
Re: Writing a RISC-V Emulator from Scratch
#13> This is the book for writing a 64-bit RISC-V emulator from scratch in Rust. Next I want to see the book for writing a 64-bit RISC-V emulator from rust in Scratch ;) The upper case S in the title made me believe for a second that they did it in Scratch :)
Since I got into programming with Scratch, every time I see it capitalized in a HN title I get my hopes up that someone made something really cool in it. Alas, it never happens.
This [0] project might be one of my favourite ones I've seen in Scratch. I don't know how they managed to correctly keep everything together, considering the size of some of the internals.
But it does do almost everything I would expect.
Re: Writing a RISC-V Emulator from Scratch
#14Thanks for your interest! I'm an author of this book. This book is very beginning as you mentioned and I'm still working on it. I already succeeded to run xv6 in my RISC-V emulator and wrote a blog post "Made a RISC-V Emulator Running Xv6": https://d0iasm.github.io/blog/risc-v/2020/04/03/xv6-on-my-ri... I have 2 different RISC-V emulators and its goals are different: rvemu ( https://github.com/d0iasm/rvemu ): Can run…
Could you please elaborate on what the differences between the two implementations are?
Re: Writing a RISC-V Emulator from Scratch
#15Thanks for your interest! I'm an author of this book. This book is very beginning as you mentioned and I'm still working on it. I already succeeded to run xv6 in my RISC-V emulator and wrote a blog post "Made a RISC-V Emulator Running Xv6": https://d0iasm.github.io/blog/risc-v/2020/04/03/xv6-on-my-ri... I have 2 different RISC-V emulators and its goals are different: rvemu ( https://github.com/d0iasm/rvemu ): Can run…
Could you please elaborate on what the differences between the two implementations are?
The main difference between them is the number of instructions are supported. Rvemu supports RV64GC, while rvemu-for-book will support RV64I and instructions that xv6 uses (e.g. mul).
Also rvemu will support a device tree but rvemu-for-book won't.
Re: Writing a RISC-V Emulator from Scratch
#16Thanks for your interest! I'm an author of this book. This book is very beginning as you mentioned and I'm still working on it. I already succeeded to run xv6 in my RISC-V emulator and wrote a blog post "Made a RISC-V Emulator Running Xv6": https://d0iasm.github.io/blog/risc-v/2020/04/03/xv6-on-my-ri... I have 2 different RISC-V emulators and its goals are different: rvemu ( https://github.com/d0iasm/rvemu ): Can run…
What does opcode 0x41 does? It's stopping the emulator when I try to run it on fib.text. Otherwise it's a pretty decent tutorial. I've also been following Stephen Marz's tutorial on bringing up a basic operating system on RiscV 64, going to use the two together.