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What Is RISC? (1993)

danluu.com

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Re: What Is RISC? (1993)

#11
post #5
post #2

This was Article 22850 of comp.arch. What's the best way to search Usenet these days? Searching for snippets of this text in Google groups came up with some of the reposts, the earliest from 1993. But the original, which must predate that, didn't show up at all when I searched for it. That seems terrible. Moreover, the interface is poor. This invaluable historical material ought to be a far more available than it is.

Have you tried DejaNews?

I did before Google destroyed it.

Re: What Is RISC? (1993)

#13
post #9

Earlier quoted context omitted.

Silly question (not much low level knowledge): which is the architecture that is today "virtually the same" for all CPUs?

I don't think there's a simple name for the modern architecture. Instead, I listed the major features off individually: > Out-of-Order, deeply pipelined, branch-predicted SIMD-accelerated load/store architectures with hidden reordering registers and multiple execution ports with 64-byte coherent caches implementing MESI-based messaging targeting Acquire/Release semantics over SMT Multithreading. In short: Intel Skyla…

Thanks for this reply. The next question I guess is whether we do this because of experience or because of debate?

Your examples of CISC instructions are specialised, as one would expect, so maybe the earlier generations of engineers simply expected more specialised machines? Ironically perhaps, with the bitcoin era, there is now more interest in specialised machines again, though my impression is hardware manifacturers are more focused on practicality. Maybe people have realised the benefit of a general CISCy-RISC architechture for the sake of not wasting time with debate?

Re: What Is RISC? (1993)

#14
post #13

Earlier quoted context omitted.

I don't think there's a simple name for the modern architecture. Instead, I listed the major features off individually: > Out-of-Order, deeply pipelined, branch-predicted SIMD-accelerated load/store architectures with hidden reordering registers and multiple execution ports with 64-byte coherent caches implementing MESI-based messaging targeting Acquire/Release semantics over SMT Multithreading. In short: Intel Skyla…

Thanks for this reply. The next question I guess is whether we do this because of experience or because of debate? Your examples of CISC instructions are specialised, as one would expect, so maybe the earlier generations of engineers simply expected more specialised machines? Ironically perhaps, with the bitcoin era, there is now more interest in specialised machines again, though my impression is hardware manifactur…

CPU Engineers always designed for the needs of their customers: with early computers having much better support for decimal arithmetic (which was popular in the 60s through 80s, but less popular today).

Overall, today's high-performance CPU programmers (and their tools: particularly their compilers) have a set of expectations, and CPU Engineers are designing their computers with those expectations in mind. That's really all there is too it.

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