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Fairylog: A Racket language aiming to be like Verilog

pinksquirrellabs.com

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Re: Fairylog: A Racket language aiming to be like Verilog

#11

Post by sametmax »

speedplane wrote: post #9
sametmax wrote: post #7

Isn't there a Python based dialect for that already ? I think it was named cirrus but I can't find any link to it. Anyway, it seems to be it would be better to make a lib for this than a whole language.

> Isn't there a Python based dialect for that already ? ... Anyway, it seems to be it would be better to make a lib for this than a whole language. FPGA programmers are quite a different breed than python developers. Things that are simple in programming languages (e.g., multiplication) can create real issues in an FPGA. I'm normally all for simplifying and unifying semantics, but with hardware programming, a split i…

Libs can track what a verilog integration system can check, and do that at a higher level. Qualcomm don't write all verilog or system c by hand, they have software generating it.

Re: Fairylog: A Racket language aiming to be like Verilog

#12

Post by sametmax »

sanxiyn wrote: post #10
sametmax wrote: post #7

Isn't there a Python based dialect for that already ? I think it was named cirrus but I can't find any link to it. Anyway, it seems to be it would be better to make a lib for this than a whole language.

> Anyway, it seems to me it would be better to make a lib for this than a whole language. This is a Racket library. The whole point of Racket is that you can make a language as a library.

I am a strong opponent to most DSL. They usually make life harder, not easier, and a regular lib is most of the time a better choice.

Re: Fairylog: A Racket language aiming to be like Verilog

#13

Post by q3k »

sametmax wrote: post #7

Isn't there a Python based dialect for that already ? I think it was named cirrus but I can't find any link to it. Anyway, it seems to be it would be better to make a lib for this than a whole language.

> Isn't there a Python based dialect for that already?

There's Migen (which is like Fairylog - a preprocessor/macro system for RTL) and MyHDL (which lets you write Verilog using a subset of 'synthesizable' Python).

Re: Fairylog: A Racket language aiming to be like Verilog

#14

Post by q3k »

sanxiyn wrote: post #4
Taniwha wrote: post #2

I'm not sure I see the point, it turns a language that looks a lot like verilog but with lots more parentheses into verilog - why not just write verilog in the first place?

It's Verilog with Racket macro! That sounds much better than Verilog with custom macro system cobbled with Perl, which is what is used in practice.

Perl? A real comment I've seen in demo code from a vendor:

  always @(X) begin // add code from "PRBS_Calculator.xls" here...

Re: Fairylog: A Racket language aiming to be like Verilog

#17

Post by tejuis »

sametmax wrote: post #11
speedplane wrote: post #9

Earlier quoted context omitted.

> Isn't there a Python based dialect for that already ? ... Anyway, it seems to be it would be better to make a lib for this than a whole language. FPGA programmers are quite a different breed than python developers. Things that are simple in programming languages (e.g., multiplication) can create real issues in an FPGA. I'm normally all for simplifying and unifying semantics, but with hardware programming, a split i…

Libs can track what a verilog integration system can check, and do that at a higher level. Qualcomm don't write all verilog or system c by hand, they have software generating it.

What are they using as source then? Please let us know more?

Re: Fairylog: A Racket language aiming to be like Verilog

#18

Post by 52-6F-62 »

tyopiuy wrote: post #15
sanxiyn wrote: post #6

Earlier quoted context omitted.

Why are they less relevant these days?

Uhh Nobody wants to do that stuff? Lol

I’d actually love to get into it. Not even a CS major.

Time hasn’t been on my side lately but I always peer in on these threads to try and improve the scope of my understanding even a little.

Re: Fairylog: A Racket language aiming to be like Verilog

#19

Post by xvilka »

Both Verilog and VHDL are a poor fit for chip design. This is why there are so many projects of higher-level hardware description languages. Chisel[1] looks to me as the best one. What I particularly like - they created an intermediate language FIRRTL[2], which might become an LLVM of hardware design. While the exact syntax might be opinionated and we need different options, the fewer wheels reinvented - the better. So at some point, it is important to create the low-level framework, on top of which many different languages can be built. You can read discussion about this particular idea here[3].

[1] https://chisel.eecs.berkeley.edu/

[2] https://bar.eecs.berkeley.edu/projects/firrtl.html

[3] https://github.com/SymbiFlow/ideas/issues/19

Re: Fairylog: A Racket language aiming to be like Verilog

#20

Post by sametmax »

tejuis wrote: post #17
sametmax wrote: post #11

Earlier quoted context omitted.

Libs can track what a verilog integration system can check, and do that at a higher level. Qualcomm don't write all verilog or system c by hand, they have software generating it.

What are they using as source then? Please let us know more?

I know that some qualcomm tools use IP described in a python dialect, and then generate the verilog out of it. They have a whole synthesis system on top of that. I assume they are not alone.
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