11–14 of 14 posts
Earlier quoted context omitted.
Chisel has better type safety than Verilog yet it's much less verbose than VHDL. Verilog is the industrial language of choice at most ASIC shops, and there are things like VerilogAMS (mixed signal) and SystemVerilog (validation) that will keep it entrenched for a long time. If you didn't have to care about ecosystem, my amateur opinion is that Chisel > VHDL > SystemVerilog > Verilog. I wasn't sure how seriously to ta…
The verilog it generates, however, is on the edge of readable, which makes it a problem if you need to debug something using waveforms. I tried to make a verilog DSL in julia, which was a lot of fun, but I got stuck on how to implement sequential logic (instead of just combinatorial logic). Even better (and should be reasonably doable with clever application of julia's macro and type system) would be to take a julia…
This is not something new, Chisel is fairly mature by now. Chisel was made by the same people who created RISCV based rocket chip. In fact rocket chip is written using Chisel https://github.com/freechipsproject/rocket-chip
In addition, Chisel is now being used industrially at SiFive and Esperanto Technologies to help design SoCs around RISC-V.
The industry lack's of wide profiles (hardware engineer with good software understanding) is really hurting any new innovative HDL
Earlier quoted context omitted.
In addition, Chisel is now being used industrially at SiFive and Esperanto Technologies to help design SoCs around RISC-V.
On this talk : - https://youtu.be/f-b4QOzMyfU?t=300 - https://youtu.be/f-b4QOzMyfU?t=492 => yes and no The industry lack's of wide profiles (hardware engineer with good software understanding) is really hurting any new innovative HDL
For what it's worth, I don't thin Chisel is really standardizable as it stands, but something like it could be.