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Intel’s Xpoint is broken

semiaccurate.com

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Re: Intel’s Xpoint is broken

#11

Post by icegreentea »

Intel will probably end of spinning this as the first (more impressive) set of numbers being estimates of the potential limits of the new technology.

Almost certainly those nice round numbers came from some engineers (or more likely, engineering manager) being pressured for 'long term performance estimates of the technology', coming up with something that seemed plausible, and then wrapped up nicely into a marketing presentation.

Or, it might be that intel actually did have something approaching each of those three claims - in three separate embodiments of the product, and is running into problems combining the traits together.

In all cases, I feel for the Intel engineers working on this project right now. Probably all cursing that original reveal.

Re: Intel’s Xpoint is broken

#12

Post by hga »

AnbeSivam wrote: post #2

From the article - > They claimed 10x the density of DRAM, it is now 4x > Latency missed by 100x, yes one hundred times, on their claim of 1000x faster, 10x is now promised > More troubling is endurance, probably the main selling point of this technology over NAND. Again the claim was a 1000x improvement, Intel delivered 1/333rd of that with 3x the endurance. From this seminar few months back - https://www.youtube.co…

Ouch!

10x latency and 3x endurance might normally satisfy the "must be 10x better" criteria to break into an existing market, but with the maturity of flash, and how memory hierarchies can ameliorate useful sets of latency requirements, this could end up being a damp squib instead of the revolution promised. 1000x endurance would have been great, 3x, who will notice?

Not the first time Intel has grossly mismanaged its technology....

Re: Intel’s Xpoint is broken

#13

Post by pas »

mankash666 wrote: post #4

The new numbers Intel is claiming, can be met by floating gate transistors that are randomly accessible (versus those arranged in bit lines and word lines like in NAND). Especially for a single level cell. No need for another materials science/physics like "x point", unless"x point" actually is just a PR spin without any new physics.

Sure, can be met, and they are random accessible, but that means a lot more wiring, right? So density goes waaay down. (Or cost goes up.) Though maybe at least they can use their "7nm process" for this too, to keep things economical.

Re: Intel’s Xpoint is broken

#14

Post by gpderetta »

hga wrote: post #12
AnbeSivam wrote: post #2

From the article - > They claimed 10x the density of DRAM, it is now 4x > Latency missed by 100x, yes one hundred times, on their claim of 1000x faster, 10x is now promised > More troubling is endurance, probably the main selling point of this technology over NAND. Again the claim was a 1000x improvement, Intel delivered 1/333rd of that with 3x the endurance. From this seminar few months back - https://www.youtube.co…

Ouch! 10x latency and 3x endurance might normally satisfy the "must be 10x better" criteria to break into an existing market, but with the maturity of flash, and how memory hierarchies can ameliorate useful sets of latency requirements, this could end up being a damp squib instead of the revolution promised. 1000x endurance would have been great, 3x, who will notice? Not the first time Intel has grossly mismanaged it…

"memory hierarchies can ameliorate useful sets of latency requirement"

Not the latency for commits to stable non-volatile storage, unless battery backed RAM is an option.

Re: Intel’s Xpoint is broken

#15

Post by hga »

gpderetta wrote: post #14
hga wrote: post #12

Earlier quoted context omitted.

Ouch! 10x latency and 3x endurance might normally satisfy the "must be 10x better" criteria to break into an existing market, but with the maturity of flash, and how memory hierarchies can ameliorate useful sets of latency requirements, this could end up being a damp squib instead of the revolution promised. 1000x endurance would have been great, 3x, who will notice? Not the first time Intel has grossly mismanaged it…

"memory hierarchies can ameliorate useful sets of latency requirement" Not the latency for commits to stable non-volatile storage, unless battery backed RAM is an option.

Or just a big enough capacitor to finish the necessary writes to flash memory. Which as I understand it is one of the things that distinguishes enterprise from consumer flash drives, and one of the reasons I use the slowest, smallest Intel enterprise flash drive for system and /home.

Re: Intel’s Xpoint is broken

#16

Post by hatsunearu »

petra wrote: post #8
mankash666 wrote: post #4

The new numbers Intel is claiming, can be met by floating gate transistors that are randomly accessible (versus those arranged in bit lines and word lines like in NAND). Especially for a single level cell. No need for another materials science/physics like "x point", unless"x point" actually is just a PR spin without any new physics.

Can you please explain this in layman's terms?

Floating gate = the switching element on a transistor acts as a capacitor and can hold charge. the basic primitive for building flash memory.

NAND SSDs which are common today are essentially rows of similar structures. Each row is a string of floating gate transistors, and to read a single bit, you gotta run the whole operation of reading the entire row.

Random access means that you can read anything anywhere without any sort of similar caveats.

Re: Intel’s Xpoint is broken

#17

Post by mankash666 »

petra wrote: post #8
mankash666 wrote: post #4

The new numbers Intel is claiming, can be met by floating gate transistors that are randomly accessible (versus those arranged in bit lines and word lines like in NAND). Especially for a single level cell. No need for another materials science/physics like "x point", unless"x point" actually is just a PR spin without any new physics.

Can you please explain this in layman's terms?

If interested, an intro to flash electronics is here: http://www.eeherald.com/section/design-guide/esmod16.html

Re: Intel’s Xpoint is broken

#18

Post by rbanffy »

AnbeSivam wrote: post #2

From the article - > They claimed 10x the density of DRAM, it is now 4x > Latency missed by 100x, yes one hundred times, on their claim of 1000x faster, 10x is now promised > More troubling is endurance, probably the main selling point of this technology over NAND. Again the claim was a 1000x improvement, Intel delivered 1/333rd of that with 3x the endurance. From this seminar few months back - https://www.youtube.co…

While certainly not breathtaking, it's an initial product on a development path. I was expecting more, but this is still an improvement.
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