>Make way for the 64-bit 128-core 1024gb RAM 8cm^2 SoC
This is already happening?
Intel Xeon Knights Landing already has an enormous 6.83cm^2 die size. It has 72 "cores," each of which has a 512-bit vector processor. In some sense, you could say that this chip has 9,216 "single precision cores." It also supports up to 384GB DDR4 RAM, which is not far from your 1024GB.
The term "core" is becoming vague, as NVIDIA refers to thousands of "CUDA cores" on its GPUs which are really vector processor elements.
China's Sunway SW26010 is also kind of a "SoC," 260 "cores" communicating via a Network-on-Chip interconnect. I think one could say that the Cell Broadband Engine processor had a similar design.
> make it practical and economical to make larger chips
I do wonder if die sizes can increase.
I'm not a hardware engineer, but my understanding is that latency is the main barrier to larger chips. The time it takes for a signal to propagate across a chip limits the clock frequency. One possibility is to replace the global synchronous clock design with an asynchronous chip design. However, from what I understand, this would make things worse because some form of synchronization is always needed - you could send back an "acknolwedge" message, but that would double the signal traffic.
On the other hand, supercomputers are regularly built with multi-socket systems and interconnects like QPI and PCIe between processors and nodes. It would seem logical to put multiple processors their interconnects on a single "SoC" and I don't know why that doesn't happen. Maybe it is because of error rates, as you say.