Designing an Ethernet Switch ASIC
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Designing an Ethernet Switch ASIC
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Re: Designing an Ethernet Switch ASIC
#2“ Cut-through vs Store-and-Forward”
I had a Google interview collapse because the last interviewer was a Principle Engineer who just couldn’t accept that a switch will ever forward a frame before reading in full and checking the FCS.
I was too much of an idiot to go along with it and instead ended up having an argument with him.
Re: Designing an Ethernet Switch ASIC
#3“ Cut-through vs Store-and-Forward” I had a Google interview collapse because the last interviewer was a Principle Engineer who just couldn’t accept that a switch will ever forward a frame before reading in full and checking the FCS. I was too much of an idiot to go along with it and instead ended up having an argument with him.
Sounds like they could have used you on that team.
Bad luck, but it at least you can walk away proud knowing it was not an issue with your technical skills. :)
Re: Designing an Ethernet Switch ASIC
#4Nice! I've been following waferspace and tiny tapeout loosely but I'm sadly not in a position to be able to work on something right now.
I'm surprised you managed to fit something like this in a TT grid square.
Re: Designing an Ethernet Switch ASIC
#5“ Cut-through vs Store-and-Forward” I had a Google interview collapse because the last interviewer was a Principle Engineer who just couldn’t accept that a switch will ever forward a frame before reading in full and checking the FCS. I was too much of an idiot to go along with it and instead ended up having an argument with him.
Cut-through is applicable in a minority of scenarios which are sometimes common. The majority of switches, especially the ones that support any advanced features at all, can't use it. Even when you can use it, you still can't use it all the time because of port conflicts.
As far as advanced features go, even adding and removing VLAN tags is a headache in a cut-through switch.
Re: Designing an Ethernet Switch ASIC
#6Nice! I've been following waferspace and tiny tapeout loosely but I'm sadly not in a position to be able to work on something right now. I'm surprised you managed to fit something like this in a TT grid square.
You can join multiple Tiny Tapeout tiles (grid squares) together to form bigger projects, which is what I did here. It's actually one of the bigger 4 grid projects.
Also how much you can fit really depends on the node the shuttle is targeting. So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm. On the other hand the gates are much slower than on Skywater 130nm.
Hopefully both programs will be around for a while, so if you are still interested when you have more time you can join the shuttle then.
Re: Designing an Ethernet Switch ASIC
#7Great project & article. Beyond the use of verilog, I couldn't find a description of the EDA stack. What tooling is used for the physical stages of design: place & route, LVS, DRC, and electrical circuit simulation (SPICE)?
Re: Designing an Ethernet Switch ASIC
#8Nice! I've been following waferspace and tiny tapeout loosely but I'm sadly not in a position to be able to work on something right now. I'm surprised you managed to fit something like this in a TT grid square.
You can join multiple Tiny Tapeout tiles (grid squares) together to form bigger projects, which is what I did here. It's actually one of the bigger 4 grid projects. Also how much you can fit really depends on the node the shuttle is targeting. So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm. On the other hand the gates ar…
You can check out the tiles for this project and their exact location on the TT chip[0].
Re: Designing an Ethernet Switch ASIC
#9Great project & article. Beyond the use of verilog, I couldn't find a description of the EDA stack. What tooling is used for the physical stages of design: place & route, LVS, DRC, and electrical circuit simulation (SPICE)?
True, I went over the EDA stack a bit in a previous article here: https://talesonthewire.com/projects/blake2s_hashing_accelera...
This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout. :)
Re: Designing an Ethernet Switch ASIC
#10Earlier quoted context omitted.
You can join multiple Tiny Tapeout tiles (grid squares) together to form bigger projects, which is what I did here. It's actually one of the bigger 4 grid projects. Also how much you can fit really depends on the node the shuttle is targeting. So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm. On the other hand the gates ar…
You can check out the tiles for this project and their exact location on the TT chip[0]. [0] https://tinytapeout.com/chips/ttgf26b/tt_um_coffeepot
Nice, thanks for posting the link.
For the people unfamiliar with the Tiny Tapeout program: everyone that gets a copy of the Tiny Tapeout chip will be getting a copy of all the ASICs on the shuttle.