Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
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Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#2[dead]
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#3They're proposing "new hardware architectures" to take advantage of this idea. Anybody with a background in GPU floating point math comment on how realistic this is?
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#4the govy uses specialized hardware that isn't sold on the market right? would something like this be useful in developing said hardware>?
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#5They're proposing "new hardware architectures" to take advantage of this idea. Anybody with a background in GPU floating point math comment on how realistic this is?
The paper is about integer multiplication, not float
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#6They're proposing "new hardware architectures" to take advantage of this idea. Anybody with a background in GPU floating point math comment on how realistic this is?
First author here. The hardware architectures are realistic - we developed & evaluated real example hardware implementations for them, validated on FPGA, and they achieved state-of-the-art ResNet performance in a deep learning accelerator system implementation compared to prior accelerators evaluated on similar FPGAs. See the associated accelerator system source code here:
https://github.com/trevorpogue/algebraic-nnhw
The hardware architectures focused on in the paper are systolic array designs, an efficient type of hardware design for matrix multiplication (e.g., the Google TPU uses this), as opposed to more SIMD-like vector architectures like GPUs. It may be possible to extend the proposed KMM algorithm to other types of hardware architectures also in future work. Regarding floating point - this work is applicable for integer matrix multiplication acceleration, it may be possible to extend the concept to floating point data types in future work also.
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#7They're proposing "new hardware architectures" to take advantage of this idea. Anybody with a background in GPU floating point math comment on how realistic this is?
[deleted]
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#8Would this work have the potential to speed up encoding/decoding of the PAR2 format[0]? This format is widely used to protect datasets against bitrot and small losses, but is held back because of the significant compute overhead when dealing with large datasets.
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#9the govy uses specialized hardware that isn't sold on the market right? would something like this be useful in developing said hardware>?
FPGAs are widely available. They are not the cheapest hardware, but they allow you to have something similar to custom silicon, but quickly and in quantities starting from 1.
Re: Karatsuba Matrix Multiplication and Its Efficient Hardware Implementations
#10They're proposing "new hardware architectures" to take advantage of this idea. Anybody with a background in GPU floating point math comment on how realistic this is?
First author here. The hardware architectures are realistic - we developed & evaluated real example hardware implementations for them, validated on FPGA, and they achieved state-of-the-art ResNet performance in a deep learning accelerator system implementation compared to prior accelerators evaluated on similar FPGAs. See the associated accelerator system source code here: https://github.com/trevorpogue/algebraic-nnh…
> systolic array designs, an efficient type of hardware design for matrix multiplication (e.g., the Google TPU uses this), as opposed to more SIMD-like vector architectures like GPUs
this is wrong. TPUv4 has tensor cores just like NVIDIA has tensor cores just like AMD has tensor cores. no one uses a systolic array because bandwidth/connectivity is much scarcer than compute. the only people that keep talking about them are academics that don't actually fab/sell chips.
https://cloud.google.com/tpu/docs/v4
https://www.nvidia.com/en-us/data-center/tensor-cores/
https://rocm.docs.amd.com/projects/rocWMMA/en/latest/what-is...
ninja edit: before you gotcha me with "a tensor core is a systolic array!!!" - most tensor cores are actually outerproduct engines not riffle shuffle engines (or whatever you wanna call the topology corresponding to a systolic array).