AMD: Microcode Signature Verification Vulnerability
1–10 of 107 posts
Re: AMD: Microcode Signature Verification Vulnerability
#2> we will not be sharing full details at this time in order to give users time to re-establish trust on their confidential-compute workloads.
What a load of shit! Confidence is earned, it does not grow back like a weed you stepped on!
Re: AMD: Microcode Signature Verification Vulnerability
#3> CPU uses an insecure hash function in the signature validation
Do we know what this "insecure hash function" is/was?
Re: AMD: Microcode Signature Verification Vulnerability
#4"A test payload for Milan and Genoa CPUs that makes the RDRAND instruction return 4"... Turns out kernel RNG belt-and-suspenders was justified?
Re: AMD: Microcode Signature Verification Vulnerability
#5> we will not be sharing full details at this time in order to give users time to re-establish trust on their confidential-compute workloads. What a load of shit! Confidence is earned, it does not grow back like a weed you stepped on!
They promised additional details in March - a month away. If they don't release that information in March then you can sharpen your pitchforks.
Re: AMD: Microcode Signature Verification Vulnerability
#6> CPU uses an insecure hash function in the signature validation Do we know what this "insecure hash function" is/was?
$5 says CRC32
Re: AMD: Microcode Signature Verification Vulnerability
#7> we will not be sharing full details at this time in order to give users time to re-establish trust on their confidential-compute workloads. What a load of shit! Confidence is earned, it does not grow back like a weed you stepped on!
I feel like this is a technical trust re-establishment, hence calling out specifically confidential-compute workloads
Re: AMD: Microcode Signature Verification Vulnerability
#8> A test payload for Milan and Genoa CPUs that makes the RDRAND instruction return 4
I would be tickled pink if the 4 was in reference to https://xkcd.com/221/
Re: AMD: Microcode Signature Verification Vulnerability
#9> A test payload for Milan and Genoa CPUs that makes the RDRAND instruction return 4 I would be tickled pink if the 4 was in reference to https://xkcd.com/221/
Of course it was.
Re: AMD: Microcode Signature Verification Vulnerability
#10"A test payload for Milan and Genoa CPUs that makes the RDRAND instruction return 4"... Turns out kernel RNG belt-and-suspenders was justified?
Yes ! I wonder what's the Windows implementation of the equivalent API.