AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
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AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
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Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#2Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#3I'd really like to see more info on the desktop G APU's. I'm not even sure if they're making a Dragon Range desktop APU, but it's what I personally am most interested in (I get that the 7000 series have fairly meager integrated graphics as is).
I realise it's a relatively unimportant market segment for them, but some info either way would be nice regardless.
Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#4 5950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. This is a curious pattern. Perhaps AMD is only binning one CCD to hit the maximum boost clocks on 16 core parts.
Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#5Off topic: I am looking for the hardware programing manual of Zen IOMMU (to map bus address to physical address), I cannot find it or what???
Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#65950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. This is a curious pattern. Perhaps AMD is only binning one CCD to hit the maximum boost clocks on 16 core parts. I have 5950X and saw this pattern, the fastest cores are though 2nd and 6th (starting from 0). I don't remember exact values from testing (with stress…
This would make sense right? You probably can't run all cores at max turbo frequency before hitting power and thermal limits. So dividing chiplets based on binning would result in good performance for 1-8 -threaded tasks while reducing chip lottery.
(But it's possible there are other reasons for the discrepancy)
Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#75950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. This is a curious pattern. Perhaps AMD is only binning one CCD to hit the maximum boost clocks on 16 core parts. I have 5950X and saw this pattern, the fastest cores are though 2nd and 6th (starting from 0). I don't remember exact values from testing (with stress…
This would make sense right? You probably can't run all cores at max turbo frequency before hitting power and thermal limits. So dividing chiplets based on binning would result in good performance for 1-8 -threaded tasks while reducing chip lottery. (But it's possible there are other reasons for the discrepancy)
The first CCD is binned for the SKU's spec, the other is whatever. This has been true for all chiplet Ryzens. Though the effect used to be more extreme, I had for example a 3900X where the second CCD only managed to run at 4.1 GHz under load, compared to ~4.4 GHz on the first CCD (and 4.6 GHz being printed on the box). That's pretty common with those.
Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#8Off topic: I am looking for the hardware programing manual of Zen IOMMU (to map bus address to physical address), I cannot find it or what???
The latest revision is from October 2022, so I assume that the many changes that have been incorporated into this revision are applicable to Zen 4:
https://www.amd.com/en/support/tech-docs/amd-io-virtualizati...
Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#95950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. This is a curious pattern. Perhaps AMD is only binning one CCD to hit the maximum boost clocks on 16 core parts. I have 5950X and saw this pattern, the fastest cores are though 2nd and 6th (starting from 0). I don't remember exact values from testing (with stress…
This would make sense right? You probably can't run all cores at max turbo frequency before hitting power and thermal limits. So dividing chiplets based on binning would result in good performance for 1-8 -threaded tasks while reducing chip lottery. (But it's possible there are other reasons for the discrepancy)
Is there optimization being done by AMD to locate the best performing chiplet on the best possible place on the bus?
Re: AMD’s Zen 4, Part 3: System Level Stuff, and iGPU
#10Apparently "CCD" stands for "core-complex die", a dumb acronym that just means "chip with cores", and different from the other "chip with i/o interconnect" you also get in a module.
It is annoyingly rare to find anybody expanding this acronym.
A meaningful definition of "CCX" is harder to find.