Memory access on the Apple M1 processor
1–10 of 278 posts
Re: Memory access on the Apple M1 processor
#2Great practical information. Nice to see people who know what they are talking about putting data out there. I hope eventually these persistent HN memes about M1 memory will die: that it's "on-die" (it's not), that it's the only CPU using LPDDR4X-4267 (it's not), or that it's faster because the memory is 2mm closer to the CPU (not that either).
It's faster because it has more microarchitectural resources. It can load and store more, and it can do with a single core what an Intel part needs all cores to accomplish.
Re: Memory access on the Apple M1 processor
#3What's the precision of these ns level measurements?
Re: Memory access on the Apple M1 processor
#4It’s a good introduction, but it’s a bit disappointing that it ends that way. I’d love to read more about what’s behind the figure and more technical info about how it might work.
Re: Memory access on the Apple M1 processor
#5Shouldn’t you choose the random numbers such that array[idx1] ^ array[idx1 + 1] are guaranteed to fall in the same cache line? Assuming that it has that. Right now some accesses cross the end of the cache line.
Re: Memory access on the Apple M1 processor
#6What is the cache line size and page table size in M1?
sysconf(_SC_PAGESIZE); /* posix */
Re: Memory access on the Apple M1 processor
#7Shouldn’t you choose the random numbers such that array[idx1] ^ array[idx1 + 1] are guaranteed to fall in the same cache line? Assuming that it has that. Right now some accesses cross the end of the cache line.
Technically you are correct but it’s expected to cross a cache line 1/16 times (or however many ints there are in a cache line). There is an implicit assumption that that is relatively infrequent enough that it shouldn’t increase the average time too much, but that assumption should be tested.
Re: Memory access on the Apple M1 processor
#8What's the precision of these ns level measurements?
The answer to that is usually very context dependant, and on what you're measuring. As long as you use a histogram first and don't blindly calculate (say) the mean it should he obvious.
Two examples( that are slightly bigger than this but the same principles apply):
If you benchmark a std::vector at insertion, you'll see a flat graph with n tall spikes at ratios of it's reallocation amount apart, and it scales very very well. The measurements are clean.
If, however, you do the same for a linked list you get a linearly increasing graph but it's absolutely all over the place because it doesn't play nice with the memory hierarchy. The std_dev of a given value of n might be a hundred times worse than the vector.
Re: Memory access on the Apple M1 processor
#9What's the precision of these ns level measurements?
Clock_gettime(CLOCK_REALTIME) on macos provides nanosecond-level precision.
Re: Memory access on the Apple M1 processor
#10What is the cache line size and page table size in M1? sysconf(_SC_PAGESIZE); /* posix */ Can you get direct processor information like LEVEL1_ICACHE_ASSOC and LEVEL1_ICACHE_LINESIZE from the M1??
`getconf PAGESIZE` returns 16384 on the base M1 MacBook Air.
The L1 cache values aren't there. The macOS `getconf` doesn't support -a (listing all variables), so they may just be under a different name.
edit: see replies for `sysctl -a` output