I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
1–10 of 52 posts
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#2Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#3Wow, any details? Somme code ? A repo ? What graphical output? VGA or hdmi ? What input? This is very intriguing...
Input happens via a N64 controller! Those are actually fairly easy to work with at a low level.
The code is not public, though I'm considering open sourcing the project when it's done. Moreover, there's a lot of additional details that I could potentially go into, so I'm considering also writing a few blogs posts with more info if people are interested!
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#4Wow, any details? Somme code ? A repo ? What graphical output? VGA or hdmi ? What input? This is very intriguing...
The screen is connected to the FPGA over VGA. The output resolution is 1024x768 @ 60Hz, but the 3D portion of the screen is rendered at 256x128 @ 30Hz. The design consists of a custom 16-bit CPU (running at 32.6Mhz) and a custom raytracing "GPU" that can handle up to 4 rays in parallel. Input happens via a N64 controller! Those are actually fairly easy to work with at a low level. The code is not public, though I'm c…
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#5Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#6Wow, any details? Somme code ? A repo ? What graphical output? VGA or hdmi ? What input? This is very intriguing...
The screen is connected to the FPGA over VGA. The output resolution is 1024x768 @ 60Hz, but the 3D portion of the screen is rendered at 256x128 @ 30Hz. The design consists of a custom 16-bit CPU (running at 32.6Mhz) and a custom raytracing "GPU" that can handle up to 4 rays in parallel. Input happens via a N64 controller! Those are actually fairly easy to work with at a low level. The code is not public, though I'm c…
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#7Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#8How is the rendering performance with large worlds?
The FPS (30Hz) is rock steady though! One of my pet peeves when doing DirectX/OpenGL development is that it's really hard to completely avoid frame drops, e.g. if the OS decides to schedule some other thread, or because the GPU driver decided to do something else than render your app. With hardware development, you can side step all of those problems. As a result, the Minecraft clone is guaranteed to not drop frames :).
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#9Earlier quoted context omitted.
The screen is connected to the FPGA over VGA. The output resolution is 1024x768 @ 60Hz, but the 3D portion of the screen is rendered at 256x128 @ 30Hz. The design consists of a custom 16-bit CPU (running at 32.6Mhz) and a custom raytracing "GPU" that can handle up to 4 rays in parallel. Input happens via a N64 controller! Those are actually fairly easy to work with at a low level. The code is not public, though I'm c…
It looks very cool! What's the GPU & CPU written in out of interest, I think I saw on your twitter you've written something to translate to verilog, is that used for this?
Re: I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM
#10Wow, any details? Somme code ? A repo ? What graphical output? VGA or hdmi ? What input? This is very intriguing...
The screen is connected to the FPGA over VGA. The output resolution is 1024x768 @ 60Hz, but the 3D portion of the screen is rendered at 256x128 @ 30Hz. The design consists of a custom 16-bit CPU (running at 32.6Mhz) and a custom raytracing "GPU" that can handle up to 4 rays in parallel. Input happens via a N64 controller! Those are actually fairly easy to work with at a low level. The code is not public, though I'm c…
Did you use your Wyre [1] language to develop it? I saw the examples on Github, and seems pretty interesting. Its cuts quite a bit of the verbosity of Verilog. I'll give it a try.