MIPS I7200 Breaks the RISC Chain
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MIPS I7200 Breaks the RISC Chain
1–10 of 10 posts
Re: MIPS I7200 Breaks the RISC Chain
#2Re: MIPS I7200 Breaks the RISC Chain
#3Re: MIPS I7200 Breaks the RISC Chain
#4Even with an adblocker, the site is unusable.
Re: MIPS I7200 Breaks the RISC Chain
#5I can get ARM microcontroller boards for $10 - $20 from ST, Microchip (nee Atmel), SiLabs, etc. More powerful ARMs in any flavor of Pi that I want.
Where do I buy a low-end interAptive or microAptive board? The Creator CI20 is super interesting, but no on-board debugger included. The LinkIt MT7688 modules don't even bring out the JTAG pins.
Re: MIPS I7200 Breaks the RISC Chain
#6Even with an adblocker, the site is unusable.
Re: MIPS I7200 Breaks the RISC Chain
#7Now if only there was somebody besides Microchip making low-cost dev kits for these things, maybe we could have some fun and get a MIPS revival. I can get ARM microcontroller boards for $10 - $20 from ST, Microchip (nee Atmel), SiLabs, etc. More powerful ARMs in any flavor of Pi that I want. Where do I buy a low-end interAptive or microAptive board? The Creator CI20 is super interesting, but no on-board debugger incl…
Re: MIPS I7200 Breaks the RISC Chain
#8Now if only there was somebody besides Microchip making low-cost dev kits for these things, maybe we could have some fun and get a MIPS revival. I can get ARM microcontroller boards for $10 - $20 from ST, Microchip (nee Atmel), SiLabs, etc. More powerful ARMs in any flavor of Pi that I want. Where do I buy a low-end interAptive or microAptive board? The Creator CI20 is super interesting, but no on-board debugger incl…
PIC32MZ are MIPS based, not quite what you want but close.
Arguably the Cortex-M0+-based D10 isn't really comparable to the PIC32, but that's sort of the point. No Arduino-sized community is going to develop around an architecture with a $50 minimum entry point... Maybe I should stop complaining about it and try to fix it :-)
Re: MIPS I7200 Breaks the RISC Chain
#9Re: MIPS I7200 Breaks the RISC Chain
#10Variable length instructions, so long as they're easy to decode, have always been present in the range of ISAs commonly called "RISC" and this new one from MIPS is no different. Except for the encoding it's basically the same thing MIPS has always been.