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So here it is, so far I wrote 2 parts:
[links redacted]
I welcome any and all critique and feedback, as I can be wrong about everything for sure.
Isn't the circuit layout going to get quite large however? How are you going to organize it? E.g. does Logisim have hierarchical views or sub-components?
Looks like a good project, a nice change from doing everything in HDL. Isn't the circuit layout going to get quite large however? How are you going to organize it? E.g. does Logisim have hierarchical views or sub-components?
Looks like a good project, a nice change from doing everything in HDL. Isn't the circuit layout going to get quite large however? How are you going to organize it? E.g. does Logisim have hierarchical views or sub-components?
Yes, it does have custom components. It gets slow with complex examples like a CPU, but not so much to become useless.
Earlier quoted context omitted.
Yes, it does have custom components. It gets slow with complex examples like a CPU, but not so much to become useless.
Good plan. Have you thought much about the instruction set yet? Any interesting features from existing commercial 8 bit processors you're going to re-implement?
I am a further into the development of the CPU then I show in the blog, as such I do have ISA already, but it's constantly changing. The control bus though, is final I think.
