51–60 of 201 posts
I worked on deep sub-micron, full custom mixed-signal integrated circuits for more than a decade, and I can't pass the first level. > Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z). Certainly: (a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied…
[flagged]
This is great! Some comments: - I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three? - I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- wit…
Oh, I didn't notice this capacitor bug, I changed it to add an enable gate for 2.4 (for context, i created 2.4 after 2.7 b/c i thought 2.7 wasn't obvious enough for some ppl). 2.4 kind of needs the enable pin b/c of how my simulation system works. Yeah, I felt pretty conflicted on the capacitors whilst building, theres actually a note about this in the capacitor info block in later levels, but I couldn't really make…
On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)
Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!
Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!
Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!
I worked on deep sub-micron, full custom mixed-signal integrated circuits for more than a decade, and I can't pass the first level. > Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z). Certainly: (a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied…
I'm a total doofus with no relevant experience and neither could I.
I worked on deep sub-micron, full custom mixed-signal integrated circuits for more than a decade, and I can't pass the first level. > Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z). Certainly: (a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied…
lol, mb. As in understand it, its that the colors of the bg make it seem like its wires when its not, I'll change the color theme a bit to fix (plz correct me if my understanding is wrong)
If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):
https://www.eecs.umich.edu/courses/eecs311/f09/tutorials/cad...
You need to have a, "Okay, I've tried 10 times, it's not working, what's the answer?" button. That will help not just us rubes who can't understand, but also in the off chance something is broken and even "correct" answers are being rejected.