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Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator

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Re: Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator

#32

Post by billforsternz »

djmips wrote: post #16

At least the 6502 has a BCD mode built in!

The Z80 does have a DAA (decimal adjust arithmetic) instruction to facilitate BCD arithmetic. I don't think I ever used it in my Z80 years and I'm not familiar with the details. Sadly I have much less experience with the 6502, I didn't even know it had a BCD mode.

Re: Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator

#36

Post by userbinator »

VLM wrote: post #4

Ironically the Z80 is a nibble ALU. That's why its so slow compared to the competition, an 8 bit add on a "2 MHz" Z80 takes as much clock time as a 8 bit add on a "1 MHz" 6809.

The Z80 is pipelined and thus has a higher latency but also higher throughput. Besides, memory was the bottleneck, in particular instruction fetches, so multicycle instructions made more sense. Related article: https://news.ycombinator.com/item?id=6341137

Re: Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator

#38

Post by adrian_b »

billforsternz wrote: post #32
djmips wrote: post #16

At least the 6502 has a BCD mode built in!

The Z80 does have a DAA (decimal adjust arithmetic) instruction to facilitate BCD arithmetic. I don't think I ever used it in my Z80 years and I'm not familiar with the details. Sadly I have much less experience with the 6502, I didn't even know it had a BCD mode.

Intel 8080 already had DAA, so it could add BCD numbers. Because there was no BCD subtraction, that had to be done by an indirect method, e.g. by doing a nines' complement before a BCD addition.

Zilog Z80 improved this, so that on it DAA could also be used after a subtraction, when it would correctly adjust the result for implementing BCD subtraction.

This was one of the Z80 improvements that were considered important at the time of its launch.

While I have never considered worthwhile to do BCD arithmetic instead of converting the decimal numbers to binary numbers, the DAA instruction on all Intel 8080 successors, including on IBM PC compatible computers, was very convenient for converting binary numbers to their ASCII character string hexadecimal representation, for printing or display purposes (because the decimal adjusting happens to add the correct ASCII offset between '0' ... '9' and 'A' ... 'F', so the conversion to ASCII can be done branchless).

Re: Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator

#39

Post by rep_lodsb »

adrian_b wrote: post #38
billforsternz wrote: post #32

Earlier quoted context omitted.

The Z80 does have a DAA (decimal adjust arithmetic) instruction to facilitate BCD arithmetic. I don't think I ever used it in my Z80 years and I'm not familiar with the details. Sadly I have much less experience with the 6502, I didn't even know it had a BCD mode.

Intel 8080 already had DAA, so it could add BCD numbers. Because there was no BCD subtraction, that had to be done by an indirect method, e.g. by doing a nines' complement before a BCD addition. Zilog Z80 improved this, so that on it DAA could also be used after a subtraction, when it would correctly adjust the result for implementing BCD subtraction. This was one of the Z80 improvements that were considered importan…

Slight correction, the correct offset is 7, and DAA only adds 6. But the trick is also adding the carry bit. This works on the 6502 in decimal mode too, e.g. https://news.ycombinator.com/item?id=6342286

On the Z80 and 8086, the code can be made one byte shorter by taking advantage of adjust-after-subtraction, which the 8080 didn't have (and on 6502 worked differently):

    CP   10      / CMP  AL,10      ;set carry if valid decimal digit
    SBC  A,69H   / SBB  AL,69H     ;0..9 => 96h..9Fh (auxC=1), 10..15 => A1h..A6h (auxC=0)
    DAA          / DAS             ;subtract 66h if auxC set, 60h if clear

Re: Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator

#40

Post by gdevic »

NetMageSCW wrote: post #26

This is a brilliant project. (My DM42 returned 9 exactly.) Blog post 6 had an error where the picture of a HP-71B (I have one and used its Forth/Assembler ROM manual to write the first HP-48 ROM decoder) where the caption says it is a 48GX (both used a Saturn CPU).

Corrected. Thank you!
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