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Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

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Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#21

Post by rowanG077 »

tubby12345 wrote: post #19
rowanG077 wrote: post #11

Earlier quoted context omitted.

I've been using Clash for about 2 years now. I just debug the clash code. As in just use the normal Haskell test tooling. The only reason I ever read the generated HDL is when I make sure I have integrated another IP correctly.

qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?

Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write this specific Verilog the tools will infer a blockram.

What Clash gives you is the power and tooling of Haskell.

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#22

Post by tubby12345 »

rowanG077 wrote: post #21
tubby12345 wrote: post #19

Earlier quoted context omitted.

qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?

Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write t…

>Clash is not HLS

i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#23

Post by Taniwha »

gnull wrote: post #12
laydn wrote: post #8

I am having trouble understanding the usefulness of all these new pseudo-HDL languages. In all the projects that I've worked on, the choice of HDL (which was 95% of the time, Verilog, for the rest, VHDL), was never actually 'important'; the language features were never critical to the completion of the project. Verilog is fully adequate for any kind of serious HDL development. What mattered were, the tooling, IDEs, d…

Clash is not pseudo, it's actual HDL. Right now it compiles to Verilog, yes, but this is minor a technicality. > the choice of HDL (which was 95% of the time, Verilog, for the rest, VHDL), was never actually 'important'; the language features were never critical to the completion of the project Because both are equally bad, and have little meaningful difference in their features. > Verilog is fully adequate for any k…

As the GP points out the problem you're up against is the tooling - to be mainstream a new language needs to be supported by the main commercial ASIC tool chains - synopsys/cadence/etc, the tools from each of the FPGA, as well at least one high performance compiled simulator (probably running on both linux and windows) - then you need coverage tools, linters or equivalents, plus you need to be able to access IP libraries in all the tapeout synthesis targets (which probably means mix and match with existing verilog and vhdl libraries and IP generators).

It's not impossible, but it is an incredibly big chicken and egg problem where most of the pieces are out of your control - the best you can do is to make highly efficient (ie synthesises well, simulates well) verilog or vhdl and hope enough people start using your tooling that the big vendors choose to implement your language as a target.

(oh and My (system)Verilog has far more types than just wire, is accepted by the big guy's tooling and generate allows me to avoid almost all copying)

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#24

Post by rowanG077 »

tubby12345 wrote: post #22
rowanG077 wrote: post #21

Earlier quoted context omitted.

Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write t…

>Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?

Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling.

HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will itself place registers, rams pipeline as necessary.

That is the reason HLS doesn't reach the performance of VHDL/Verilog, these HLS tools just aren't as good as a human making the digital circuit.

Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. Just like with VHDL or Verilog. It's just an alternative way of writing it.

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#25

Post by tubby12345 »

rowanG077 wrote: post #24
tubby12345 wrote: post #22

Earlier quoted context omitted.

>Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?

Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will i…

got it - it's like chisel. thanks

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#26

Post by gnull »

Taniwha wrote: post #23
gnull wrote: post #12

Earlier quoted context omitted.

Clash is not pseudo, it's actual HDL. Right now it compiles to Verilog, yes, but this is minor a technicality. > the choice of HDL (which was 95% of the time, Verilog, for the rest, VHDL), was never actually 'important'; the language features were never critical to the completion of the project Because both are equally bad, and have little meaningful difference in their features. > Verilog is fully adequate for any k…

As the GP points out the problem you're up against is the tooling - to be mainstream a new language needs to be supported by the main commercial ASIC tool chains - synopsys/cadence/etc, the tools from each of the FPGA, as well at least one high performance compiled simulator (probably running on both linux and windows) - then you need coverage tools, linters or equivalents, plus you need to be able to access IP libra…

I'm trying to look at one specific component here, the language itself. My claim is that as a language Clash is way better than SystemVerilog.

True, Verilog has more mature tooling and is better supported by vendors at the moment. But most of it is because Verilog is old, and because hardware people have little knowledge of (and demand for) good programming languages; not because it's a good language (maybe it's better than the other even worse languages, but it's not good by the software programming standards). It's not that Verilog is somehow inherently good for implementing tooling for it, absolutely not better than Clash.

> far more types than just wire

You mean integers and C-style structs? “Far more” is a big stretch here. And these “types” are not very useful: they are only used to decide how operators should behave on values. As far as I remember, even Verilog's assignment doesn't care about types, as long as left- and right-hand side have the same number of bits, the assignment is allowed.

> generate allows me to avoid almost all copying

At the cost of: extra work (you're essentially implementing polymorphism by hand), inferior readability, increased risk of making mistakes, no support from the compiler. Generate can be almost perfectly replaced by code generation in Python.

Seriously, look at the way Clash allows parametrizing things, you will be impressed.

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#27

Post by rowanG077 »

tubby12345 wrote: post #25
rowanG077 wrote: post #24

Earlier quoted context omitted.

Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will i…

got it - it's like chisel. thanks

Not exactly. Chisel is a DSL while clash is not. But it's at the same level of circuit design abstraction.

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#28

Post by rowanG077 »

tubby12345 wrote: post #25
rowanG077 wrote: post #24

Earlier quoted context omitted.

Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will i…

got it - it's like chisel. thanks

Looking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL/Verilog. Clash is a compiler closely based on GHC that compiles Haskell code, not a DSL defined within Haskell, to VHDL/Verilog.

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#29

Post by tubby12345 »

rowanG077 wrote: post #28
tubby12345 wrote: post #25

Earlier quoted context omitted.

got it - it's like chisel. thanks

Looking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL/Verilog. Clash is a compiler closely based on GHC that compiles Haskell code, not a DSL defined within Haskell, to VHDL/Verilog.

you're saying seemingly contradictory things (that would best be resolved for me if i just dug into clash, so i will):

>HLS generally means you compile a very high level description of computation to VHDL/Verilog.

...

>Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit.

...

>Clash is a compiler closely based on GHC that compiles Haskell code

what does it mean for clash to compile haskell code but not to come up with a digital circuit? haskell code (afaik) doesn't represent combinational or sequential logic. well maybe it does using clash (thanks to haskell crazy metaprogramming faciilities) but then what does it mean to "compile"? verilog isn't compiled, it's still synthesized to gates and luts and whatever right? what does clash compile to natively if not verilog/vhdl (which then gets synthesized)?

Re: Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design

#30

Post by rowanG077 »

tubby12345 wrote: post #29
rowanG077 wrote: post #28

Earlier quoted context omitted.

Looking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL/Verilog. Clash is a compiler closely based on GHC that compiles Haskell code, not a DSL defined within Haskell, to VHDL/Verilog.

you're saying seemingly contradictory things (that would best be resolved for me if i just dug into clash, so i will): >HLS generally means you compile a very high level description of computation to VHDL/Verilog. ... >Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. ... >Clash is a compiler closely based on GHC that compiles Haskell code what do…

It's not contradictory. A Haskell function(modulo io and boundless recursion) gets compiled to combinational logic without registers. a digital circuit circuit in clash are normal Haskell function combined together with registers and other combinators. Clash can compile to an executable as well as to hardware. The executable is a cycle accurate simulation of the circuit.
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